XAUI-PM-U1 Lattice, XAUI-PM-U1 Datasheet - Page 22

• Manufacturer Part Number: XAUI-PM-U1
• Description: Development Software XAUI 10Gb Ethernet
• Manufacturer: Lattice

Specifications of XAUI-PM-U1

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
XAUI IP Core User’s Guide
The following files are generated in the user’s project directory (\xaui_test in Figure 16):
• <username>.lpc - IP parameter file (may be directly modified by user).
• <username>.ngo - synthesized and mapped IP core.
• <username>_bb.v - black box module wrapper for synthesis.
• <username>_inst.v - example of instantiation template to be included in user’s design.
• <username>_beh.v - behavioral simulation model for IP core configuration username.
These are all of the files needed by the user to implement and verify the XAUI IP core in their top-level design. The
following additional files providing IP core generation status information and command line generation capability
are generated in the user’s project directory:
• <username>_generate.tcl - created when GUI “Generate” button is pushed, invokes generation, may be run from
command line.
• <username>_generate.log - ispLEVER synthesis and map log file.
• <username>_gen.log - IPexpress IP generation log file.
The \xaui_core_eval and subtending directories provide files supporting XAUI core evaluation. The \xaui_core_eval
directory shown in Figure 16 contains files/folders with content that are constant for all configurations of the XAUI
core. The \<username> subfolder (\xaui_core0 in this example) contains files/folders with content specific to the
username configuration.
The \xaui_core_eval directory is created by IPexpress the first time the core is generated and updated each time
the core is regenerated. A \<username> directory is created by IPexpress each time the core is generated and
regenerated each time the core with the same file name is regenerated. A separate \<username> directory is gen-
erated for cores with different names, e.g. \core1, \core2, etc.
Instantiating the Core
The generated XAUI IP core is provided in Lattice’s proprietary .ngo format, which is independent of the HDL used
to capture the rest of the user’s design. The generated XAUI IP core package includes black-box (<user-
name>_bb.v) and instance (<username>_inst.v) templates that can be used to instantiate the core in a top-level
design. An example RTL top-level reference source file is provided in \<project_dir>\xaui_core_eval\<user-
name>\src. Customers may use this top-level reference as the starting template for the top-level for their complete
design.
Running Functional Simulation
The functional simulation includes a configuration-specific behavioral model of the XAUI core (<username>_beh.v)
that is instantiated in an FPGA top-level along with DDR IO logic for the XGMII interface. This FPGA top is instanti-
ated in an eval testbench that configures the XAUI core registers. The testbench test pattern generator sources
data to the XAUI core via the XGMII interface. The output of the PCS core is then serially loopback to the XAUI
core. The receive data at the XGMII interface is then checked against the expected data.
Users may run the eval simulation by doing the following:
®
1. Open ModelSim
.
2. Under the File tab, select Change Directory and choose folder
\<project_dir>\xaui_core_eval\<username>\sim\modelsim.
3. Under the Tools tab, select Execute Macro and execute one of the ModelSim “do” scripts shown.
The simulation waveform results are displayed in the ModelSim Wave window.
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