DS33X42DK Maxim Integrated Products, DS33X42DK Datasheet - Page 337
DS33X42DK
Manufacturer Part Number
DS33X42DK
Description
Power Management Modules & Development Tools Ethernet Over PDH Ma PDH Mapping Devices
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33X11.pdf
(375 pages)
Specifications of DS33X42DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Each MII Interface Transmit Port has its own TX_CLK and data interface. The data TXD [3:0] operates
synchronously with TX_CLK. The LSB is presented first. TX_CLK should be 2.5MHz for 10Mbps operation and
25MHz for 100Mbps operation. TX_EN is valid at the same time as the first byte of the preamble. In DTE Mode
TX_CLK is input from the external PHY. In DCE Mode, the device provides TX_CLK, derived from an external
reference (SYSCLKI).
In Half-Duplex (DTE) Mode, the device supports RX_CRS and COL signals. RX_CRS is active when the PHY
detects transmit or receive activity. If there is a collision as indicated by the COL input, the device will replace the
data nibbles with jam nibbles. After a “random“ time interval, the frame is retransmitted. The MAC will try to send
the frame a maximum of 16 times. The jam sequence consists of 55555555h. Note that the COL signal and
RX_CRS can be asynchronous to the TX_CLK and are only valid in half duplex mode.
Figure 11-20. MII Transmit Functional Timing
Figure 11-21. MII Transmit Half Duplex with a Collision Functional Timing
Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is
2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation. RX_DV is asserted by the PHY from the first
Nibble of the preamble in 100Mbps operation or first nibble of SFD for 10Mbps operation. The data on RXD[3:0] is
not accepted by the MAC if RX_DV is low or RX_ERR is high (in DTE mode). RX_ERR should be tied low when in
DCE Mode.
Figure 11-22. MII Receive Functional Timing
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
RX_CRS
TXD[3:0]
TX_EN
COL
TX_CLK
RX_CLK
TX_CLK
RXD[3:0]
RX_CRS
TXD[3:0]
TX_EN
P
R
P
P
E
R
R
A
M
E
E
B
L
A
A
E
J
E
E
J
J
M
M
J
J
B
B
J
L
L
J
J
E
E
F
F
C
C
S
S
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