MAX17480EVKIT+ Maxim Integrated Products, MAX17480EVKIT+ Datasheet - Page 10

• Manufacturer Part Number: MAX17480EVKIT+
• Description: Power Management Modules & Development Tools EVAL KIT FOR MAX17480
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

On startup, the MAX17480 slews the target for all three
DACs from ground to the boot voltage set by the SVC
and SVD pin voltage levels. While the output is still
below regulation, the SVC and SVD levels can be
changed and the MAX17480 will set the DACs to the
new boot voltage. Once the programmed boot voltage
is reached and PWRGD goes high, the MAX17480
stores the boot VID. Changes in the SVC and SVD set-
tings do not change the output voltage once the boot
VID is stored. When PGD_IN goes high, the MAX17480
exits boot mode, and the three DACs can be indepen-
dently set to any voltage in the VID table through the
serial interface.
If PGD_IN goes from high to low any time after the boot
VID is stored, the MAX17480 sets all three DACs back
to the voltage of the stored boot VID. Table 6 shows the
boot-voltage codes.
Each phase of the MAX17480 core-supply SMPS
includes one transconductance amplifier for AC droop.
The amplifiers’ inputs are generated by summing the
respective current-sense inputs, which differentially
sense the voltage across the inductor’s DCR. The
transconductance amplifier’s output (FBAC) connects
to the feedback input (FBDC) though a capacitor (C63
for phase 1 and C64 for phase 2), resulting in AC-
coupling of the ripple voltage with no DC voltage, giving
no DC droop in the default configuration.
For applications that require voltage positioning, install
the resistor between FBAC and FBDC (R60 for phase 1
and R61 for phase 2). The resulting DC droop is a frac-
tion of the AC-droop setting. Refer to the MAX17480 IC
data sheet for detailed information on setting AC and
DC droop.
MAX17480 Evaluation Kit
Table 6. Boot-Voltage Codes
10
______________________________________________________________________________________
SVC
0
0
1
1
Reduced Power-Dissipation
SVD
0
1
0
1
Voltage Positioning
BOOT VOLTAGE
V
Boot Voltage
BOOT
1.1
1.0
0.9
0.8
(V)
One interesting experiment is to subject the output to
large, fast load transients and observe the output with
an oscilloscope. Accurate measurement of output rip-
ple and load-transient response invariably requires that
ground clip leads be completely avoided and that the
probe be removed to expose the GND shield, so the
probe can be directly grounded with as short a wire as
possible to the board. Otherwise, EMI and noise pickup
corrupt the waveforms.
Most benchtop electronic loads intended for power-
supply testing lack the ability to subject the DC-DC
converter to ultra-fast load transients. Emulating the
supply current (di/dt) at the CPU VCORE pins requires
at least 500A/µs load transients. An easy method for
generating such an abusive load transient is to install a
power MOSFET at the N7 location and install resistor
R35 between 5mΩ and 10mΩ to monitor the transient
current. Then drive its gate (TP1) with a strong pulse
generator at a low duty cycle (< 5%) to minimize heat
stress in the MOSFET. Vary the high-level output volt-
age of the pulse generator to vary the load current.
To determine the load current, you might expect to
insert a meter in the load path, but this method is pro-
hibited here by the need for low resistance and induc-
tance in the path of the dummy-load MOSFET. To
determine how much load current a particular pulse-
generator amplitude is causing, observe the current
through inductor L1. In the buck topology, the load cur-
rent is approximately equal to the average value of the
inductor current.
When SHDN goes low (JU4 = GND), the MAX17480
immediately enters the shutdown mode and PWRGD is
pulled low immediately—the drivers are disabled, the
reference turns off, the supply currents drop to approxi-
mately 1µA (max), and all three outputs are discharged
through 20Ω internal discharge FETs through the CSN
pin for the core SMPSs and through the OUT3 pin for
the NB SMPS.
When an overvoltage or undervoltage fault condition
occurs on the core SMPS, the NB SMPS immediately
shuts down. To clear the fault latch and reactivate the
controller, toggle SHDN or cycle V
Table 7).
Load-Transient Experiment
Jumper Settings
Shutdown (SHDN)
CC
power (see