MAX17480EVKIT+ Maxim Integrated Products, MAX17480EVKIT+ Datasheet - Page 8

• Manufacturer Part Number: MAX17480EVKIT+
• Description: Power Management Modules & Development Tools EVAL KIT FOR MAX17480
• Manufacturer: Maxim Integrated Products

Specifications of MAX17480EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX17480 EV kit consists of one dual-phase SMPS
for the CPU core, and one 4A internal switch SMPS for
the northbridge core. The SMPS buck-regulator design
is optimized for a 300kHz switching frequency per
phase and output-voltage settings around 1.200V. At
V
approximately 30% (LIR = 0.3). The MAX17480 con-
troller interleaves both phases, resulting in 180° out-of-
phase operation that minimizes the input and output
filtering requirements. The MAX17480 controller shares
the current between the two phases, supplying up to
18A per phase. The 4A internal-switch SMPS operates
at 600kHz switching frequency and delivers up to 4A.
The MAX17480 EV kit is configured to evaluate the
MAX17480 IC in combined-mode operation. In com-
bined mode, core SMPSs (SMPS1 and SMPS2) are
combined into a single output (VCORE0). The EV kit
can be configured to operate in separate mode to pro-
vide two outputs, VCORE0 (SMPS1) and VCORE1
(SMPS2). See the Separate-Mode Operation section for
configuration details.
Inside the MAX17480 are three 7-bit digital-to-analog
converters (DACs). Each DAC can be individually pro-
grammed to different voltage levels through the serial-
MAX17480 Evaluation Kit
Table 3. SW3 Dynamic Output Test with High-Speed I
N/A = Not applicable.
Table 4. SW4 Dynamic Output Test with High-Speed I
N/A = Not applicable.
8
OUT
Detailed Description of Hardware
_______________________________________________________________________________________
STEP
STEP
= 1.200V and V
1
2
3
1
2
3
4
5
6
7
8
ADDRESS
ADDRESS
Setting the Output Voltage
0xC4
0xC8
0xCE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
IN
= 12V, the inductor ripple is
DATA
DATA
0xCC
0xCC
0x9C
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7-Bit DAC
Set all DACs to 0V (Core 0, Core 1, and NB)
Wait 1ms
Set all DACs to 1.55V (Core 0, Core 1, and NB)
Set SHDN and PGD_IN to logic-low
Wait 10ms
Set SVC to logic-low and SVD to logic-high
Set SHDN to logic-high
Wait 2ms
Set PGD_IN to logic-high
Wait 10µs
Set all DACs to 1.2V (Core 0, Core 1, and NB)
interface bus. The DAC sets the target for the output
voltage for the SMPSs. The available DAC codes, and
resulting output voltages, are compatible with the AMD
SVI specifications (see Table 5).
The MAX17480 supports the 2-wire write-only serial-
interface bus, as defined by the AMD serial VID inter-
face specification. The serial interface is similar to the
high-speed 3.4MHz I
mode sequence. The bus consists of a clock line (SVC)
and a data line (SVD). The CPU is the bus master and
the MAX17480 is the slave.
The MAX17480 serial interface works from 100kHz to
3.4MHz. In the AMD mobile application, the bus runs at
3.4MHz. In the MAX17480 EV kit, the serial interface
operates at 400kHz when commands are sent through
the EV kit software. When using the preprogrammed
SW switches, the serial interface operates at 1.7MHz.
The serial interface is active only after PGD_IN goes
high in the startup sequence. The CPU sets the VID
voltage of the three internal DACs and the PSI_L bit
through the serial interface after PGD_IN goes high.
During the startup sequence, the SVC and SVD inputs
serve an alternate function to set the 2-bit boot VID for
all three DACs while PWRGD is low, and are in the
serial-interface mode when PGD_IN is high.
2
2
C Interface
C Interface
DESCRIPTION
DESCRIPTION
2-Wire Serial Interface (SVC, SVD)
2
C bus, but without the master-