STEVAL-ISV009V1 STMicroelectronics, STEVAL-ISV009V1 Datasheet

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MPPT algorithm Introduction SPV1020 is a monolithic DC-DC boost converter designed to maximize the power generated by photovoltaic panels independently of temperature and amount of solar radiation. The optimization of the power conversion is obtained with ...

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Contents Contents 1 Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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AN3392 13.5 Input voltage capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Figure 21. SPI interface: master slaves connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 22. Frame structure: register read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 23. Pin connection top view PSSO36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 24. STEVAL-ISV009v1 schematic connections (PSSO36 package Figure 25. PCB layout example (top view Figure 26. PCB layout example (bottom view Figure 27. ISV009v1 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 28 ...

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AN3392 List of tables Table 1. Data format for words longer than 8 bits ...

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Application overview 1 Application overview Following picture shows the typical architecture of a photovoltaic system for grid connected application and composed by the photovoltaic field and the electronic part: Figure 2. SPV1020, output series connection Photovoltaic field is composed by ...

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AN3392 Anti-island control, a safety control forcing the system disconnection from the grid ● when this is off for maintenance. Inverter control, for transforming the DC power generated by the system in the AC ● power compatible (in terms of ...

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Application overview Figure 4. Photovoltaic panel for a distributed architecture 8/52 Doc ID XXXXX Rev 1 AN3392 ...

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AN3392 2 Application information A step-up (or boost) converter is a switching DC-DC converter able to generate an output voltage higher than (or at least equal to) the input voltage. Figure 5. Step-up converter single ended architecture The switching element ...

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Application information Where “D” is the duty cycle [T element. Boost applications can work in two main cases: ● Continuous Mode (CM) and; ● Discontinuous Mode (DCM); depending if the current on inductor becomes null (DCM), or not (CM), within ...

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AN3392 3 SPV1020 description SPV1020 designed to control a boost with a 4 phases interleaved topology supplied by photovoltaic panels 4-phases topology the inductor-switch-diode branch is cloned 3 times and the resulting 4 branches are ...

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SPV1020 description Figure 9. Synchronous rectification and zero crossing block Finally, in order to reduce the whole BOM, SPV1020 integrates the 8 switching elements. Figure 10. Boost IL-4 and SPV1020 Even if the interleaved topology increases the BOM and the ...

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AN3392 4 Output voltage ripple Assuming a resistive load, the output voltage ripple is directly tied to the output current ripple single ended architecture, the output current is the current flowing on the inductor when it re-circulates through ...

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Application efficiency 5 Application efficiency Designing a boost application a typical constraint is the maximum output current ripple. Once frequency, input and output voltage are defined, this constraint directly affects the inductance value to place in the application: Inductance value ...

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AN3392 6 SPV1020 functionalities Operating modes SPV1020 works among 3 main operating modes/states, depending on the voltage provided by the supply source and by the previous mode/state: ● OFF state, ● BURST mode, ● Normal (or MPPT) mode. Figure 12. ...

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OFF state 7 OFF state SPV1020 has a UVLO (under voltage lockout) with hysteresis of 500mV. The two thresholds are 6.5 V (UVLO_H) for turning on and 6.0 V for turning off (UVLO_L). At power up, until the supply source ...

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AN3392 8 Burst mode This mode guarantees a correct start-up for SPV1020, avoiding voltage oscillation. After the power supply connection, the converter starts to work when input voltage becomes higher than 6.5 V (ULVO_H). Burst Mode contains 4 internal states, ...

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Normal/MPPT mode 9 Normal/MPPT mode This mode guarantees the maximum power extraction from a photovoltaic input supply by executing an MPPT algorithm. MPPT algorithm generates a voltage reference (Vref) for a PWM generator. The resulting waveform (which Duty Cycle is ...

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AN3392 Figure 16. PV panels, voltage-power and voltage-current curves The Voltage-Current curve shows all the available working point of the PV panel at a given solar irradiation. The Power- Voltage curve is derived by the Voltage-Current curve, plotting the product ...

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Normal/MPPT mode Increasing or decreasing DC depends on the update done in previous step (Sign) and by the trend of the input power. In fact, MPPT algorithm compares the current input power (P computed in the previous step (P previous ...

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AN3392 Figure 19. Normal/MPPT mode, DCM vs. CM FSM In case of DCM, input current could be negligible and its sampled value could be strongly affected by the noises caused by the switching elements. So, input power is computed as ...

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Normal/MPPT mode Figure 20. Input voltage partitioning, sample circuit 22/52 Doc ID XXXXX Rev 1 AN3392 ...

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AN3392 10 Voltage regulation In order to protect both the device itself and the load, SPV1020 implements a dual control on the output voltage (Vout). Control on Vout is done through Vout_sns pin, connected to Vout by a resistive partitioning ...

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Voltage regulation SPV1020 implements an internal control guaranteeing the current balance among the 4 branches, monitoring the current flowing on each branch with a maximum offset of 350mA. 10.4 SPI, serial peripheral interface The SPV1020 embeds a 4-pin compatible SPI ...

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AN3392 Figure 22. Frame structure: register read operation The SPV1020 register file is accessible by the host through the SPI bus. Thus, the host can read some register of SPV1020 control parameters. Each data frame includes at least one command ...

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Voltage regulation Table 2 shows a list of commands. Each command addresses a memory location of a certain width and sets the direction of the related data. Table 2. Commands list Code (Hex Read current ...

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AN3392 11 Pin description Table 3. Pin description Pin Name (Psso36) 34 VIN 7,8,17- VOUT 20,29,30 12,13,24,25 PGND 1 SGND 10,11,14,15, LX1…4 22,23,26,26 9,16,21,28 CB1…4 31 XCS 32 SPI_DATA_IN 33 SPI_CLK 35 VIN_SNS 36 VIN_SNS_M 2 PZ_OUT 3 VOUT_SNS 4 ...

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Pin description 11.1 Pin connection Figure 23. Pin connection top view PSSO36 28/52 Doc ID XXXXX Rev 1 AN3392 ...

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AN3392 12 Absolute maximum ratings Table 4. Maximum ratings Symbol VIN VOUT PGND SGND VOUT_SNS LX1….4 CB1…4 VREG VIN_SNS XCS OSC_IN PZ_OUT SPI_DATA_OUT SPI_CLK SPI_DATA_IN VIN_SNS_M Parameter Power supply Power supply Power ground Signal ground Analog input Analog input Analog ...

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... Following chapters will refer to the connections and component labels showed in the schematic below: Figure 24. STEVAL-ISV009v1 schematic connections (PSSO36 package) Please note that dashed connections on OSCIN pin are alternative: if default switching frequency will be used (100kHz), then a short between pins OSCIN and VREG is suggested ...

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AN3392 13.1 Power and thermal considerations SPV1020 performances are strongly impacted by the power capability of the PWSSO36 package, which depends from the application board as well. According to the technical note TN0054 R of PwSSO36 can be reduced up ...

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External component selection Considering the maximum duty cycle (90%): Taking into account the overcurrent threshold (4.5 A): Finally, inductance should be chosen according to the following formula: A safer choice should replace Vmp by Voc of the panel. Usually, inductances ...

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AN3392 13.4 Internal voltage rail capacitors tank capacitor used to guarantee the voltage level ( the internal regulated voltage of the SPV1020. Suggested value is 470 nF and it isn’t application dependant. Same voltage range ...

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External component selection Assuming negligible the current flowing through pin Vin_sns, maximum power dissipation on the series R1+R2 is: As empiric rule, R1 and R2 should be selected according to: Note: In order to guarantee the proper functionality of pin ...

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AN3392 Maximum voltage of this capacitor is strictly dependent by the output voltage range. SPV1020 can support so, suggested maximum voltage for these capacitors higher. Low-ESR capacitors are good choices to increase ...

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External component selection 13.10 Output voltage sensing capacitor C10 is placed in parallel to R4 and as close as possible to pin Vout_sns. Its role is to make as stable as possible the voltage sensed by pin Vout_sns. Maximum Voltage: ...

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AN3392 D3 has to be chosen taking care mainly to its low forward voltage in order to impact as less as possible the system efficiency. Maximum forward current will be according to the maximum current sink by SPV1020: a safe ...

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Layout guidelines 14 Layout guidelines PCB layout is very important in order to minimize noise, high frequency resonance problems and electromagnetic interference. Paths between each inductor and relative pin must be designed with the same resistance. Different resistance between the ...

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AN3392 Figure 26. PCB layout example (bottom view) Doc ID XXXXX Rev 1 Layout guidelines 39/52 ...

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BOM 15 BOM The following table shows a possible list of external components to configure SPV1020 application with Voc = 30 V, Imp = 9 A, Vout_max = 36 V and Fsw = 100 kHz. Of course, suppliers ...

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AN3392 Table 5. Bill of material (continued) Component Name D1, D2 Controller bypass diodes J35 Voltage boost controller J36 SPI I/F connector 600W, 40V D4 biidirectional protection transil J47, J48 Output connector J40 Alternative input connector L5 Output current ripple ...

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... Ns_min is suggested. Also, considering that SPV1020 is a voltage boost controller it is required that maximum input voltage (Vo of the each PV panel) must be lower than its output voltage. So, maximum number of devices in series is also limited by the following rule: 42/52 (STEVAL-ISV009V1 ...

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AN3392 Appendix B SPV1020 parallel and series connection Output pins of SPV1020s can be connected both in parallel and in series. In both cases the output power (Pout) will depend on light irradiation of each panel (Pin), application efficiency and ...

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SPV1020 parallel and series connection B.1 SPV1020 parallel connection This topology guarantees the desired output voltage even only one of the panels is irradiated. Of course, the constraint of this topology is that Vout is limited to the SPV1020 technology ...

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AN3392 So: Pout Each SPV1020 will contribute to the output power providing Ioutx according to the irradiation of its panel. Also, desired Vout will be guaranteed if at least one of the 3 PV panels provides enough power to turn ...

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SPV1020 parallel and series connection In case the irradiation is the same for each panel: So, For example, assuming, Pout = 90 W and, if desired Vout = 90 V then Voutx = 30V. Lower irradiation for one panel, for ...

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AN3392 Two of the SPV1020s (1 2. SPV1020 is a boost controller, so Voutx must be higher than Vinx, otherwise the SPV1020 Note: turns off and the input power is transferred to the output stage trough by pass diode D1 ...

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SPV1020 parallel and series connection In this case the system is at the limit, in fact a lower irradiation on will impact Vout1 and/or Vout3 that are anyway at the limit (40V) imposed by R3/R4 partitioning. Example 3: Panel 2 ...

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AN3392 16 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...

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Package mechanical data Figure 30. PowerSSO-36™ package dimensions 50/52 Doc ID XXXXX Rev 1 AN3392 ...

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AN3392 17 Revision history Table 7. Document revision history Date 02-May-2011 Revision 1 Initial release Doc ID XXXXX Rev 1 Revision history Changes 51/52 ...

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