STEVAL-IFS001V1 STMicroelectronics, STEVAL-IFS001V1 Datasheet
STEVAL-IFS001V1
Specifications of STEVAL-IFS001V1
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STEVAL-IFS001V1 Summary of contents
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Digital Output Low Voltage Linear Accelerometer Features ■ 2.16V TO 3.6V SINGLE SUPPLY OPERATION ■ 1.8V COMPATIBLE IOs 2 ■ I C/SPI DIGITAL OUTPUT INTERFACES ■ PROGRAMMABLE BIT DATA REPRESENTATION ■ INTERRUPT ACTIVATED BY ...
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Contents 1 Block Diagram & Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ...
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LIS3LV02DQ 7.2 OFFSET_X (16h ...
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Mechanical Characteristics derived from measurement in the -40°C to +85°C temperature range 8.3 Electro-Mechanical characteristics at 25° ...
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LIS3LV02DQ 1 Block Diagram & Pin Description 1.1 Block diagram Figure 1. Block Diagram SELF TEST 1.2 QFPN-28 Pin description Figure 2. Pin Connection 1 Z DIRECTION OF THE DETECTABLE ACCELERATIONS Σ∆ ...
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Block Diagram & Pin Description Table 1. Pin description Pin Reserved SCL/SPC 13 14 Reserved 19 20 Reserved 21-28 6/42 Name NC Internally ...
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LIS3LV02DQ 2 Mechanical and Electrical specifications 2.1 Mechanical characteristics Table 2. Mechanical Characteristics (All the parameters are specified @ Vdd=2.5V, T=25°C unless otherwise noted) Symbol Parameter FS Measurement range Dres Device Resolution So Sensitivity Sensitivity Change Vs TCS0 Temperature Zero-g ...
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Mechanical and Electrical specifications Table 2. Mechanical Characteristics (continued) (All the parameters are specified @ Vdd=2.5V, T=25°C unless otherwise noted) Symbol Parameter NL Non Linearity CrAx Cross Axis V Self test Output Change System Bandwidth Operating ...
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LIS3LV02DQ Table 3. Mechanical Characteristics (All the parameters are specified @ Vdd=3.3V, T=25°C unless otherwise noted) Symbol Parameter FS Measurement range Dres Device Resolution So Sensitivity Sensitivity Change Vs TCS0 Temperature Zero-g Level Offset Off 4,5 Accuracy Zero-g Level Offset ...
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Mechanical and Electrical specifications Table 3. Mechanical Characteristics (continued) (All the parameters are specified @ Vdd=3.3V, T=25°C unless otherwise noted) Symbol Parameter V Self test Output Change System Bandwidth Operating Temperature Top Range Wh Product Weight ...
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LIS3LV02DQ 2.2 Electrical characteristics Table 4. Electrical Characteristics (All the parameters are specified @ Vdd=2.5V, T=25°C unless otherwise noted) Symbol Parameter Vdd Supply voltage Vdd_IO I/O pads Supply voltage Idd Supply current Digital High level Input VIH voltage Digital Low ...
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Mechanical and Electrical specifications 2.3 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is ...
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LIS3LV02DQ 2.4 Terminology 2.4.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of ...
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Functionality 3 Functionality The LIS3LV02DQ is a high performance, low-power, digital output 3-axis linear accelerometer packaged in a QFN package. The complete device includes a sensing element and an IC interface able to take the information from the sensing ...
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LIS3LV02DQ 3.3 Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (Off). The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on, the trimming parameters ...
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Application Hints 4 Application Hints Figure 3. LIS3LV02DQ Electrical Connection 10uF 100nF Vdd GND The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 ...
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LIS3LV02DQ 5 Digital Interfaces The registers embedded inside the LIS3LV02DQ may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped ...
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Digital Interfaces 2 5.1 Operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is ...
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LIS3LV02DQ function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line slave receiver doesn’t ...
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Digital Interfaces bit 8-15 : data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15 : data DO(7:0) (read mode). This is the data that will be read from the ...
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LIS3LV02DQ 5.2.2 SPI Write Figure 7. SPI Write protocol CS SPC SDI The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 ...
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Digital Interfaces The SPI Read command is performed with 16 clock pulses: bit 0 : READ bit. The value is 1. bit bit. When 0 do not increment address, when 1 increment address in multiple reading. ...
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LIS3LV02DQ 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address. Table 8. Registers address map Reg. Name WHO_AM_I OFFSET_X OFFSET_Y OFFSET_Z GAIN_X GAIN_Y GAIN_Z CTRL_REG1 CTRL_REG2 ...
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Register mapping Table 8. Registers address map (continued) Reg. Name FF_WU_THS_H FF_WU_DURATION DD_CFG DD_SRC DD_ACK DD_THSI_L DD_THSI_H DD_THSE_L DD_THSE_H Registers marked as reserved must not be changed. The writing to those registers may cause permanent damages to the device. ...
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LIS3LV02DQ 7 Register Description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers 7.2 to 7.7 contain the factory calibration values not necessary to change their ...
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Register Description 7.5 GAIN_X (19h) GX7, GX0 Digital Gain Trimming for X-Axis 7.6 GAIN_Y (1Ah) GY7, GY0 Digital Gain Trimming for Y-Axis 7.7 GAIN_Z (1Bh) GZ7, GZ0 Digital Gain Trimming for Z-Axis 7.8 CTRL_REG1 (20h) Power Down Control PD1, ...
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LIS3LV02DQ ST bit is used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to check the ...
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Register Description trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again ...
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LIS3LV02DQ 7.11 HP_FILTER_RESET (23h) Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. Read data is not significant. 7.12 STATUS_REG (27h) ZYXOR X, Y and Z axis Data Overrun ZOR Z axis Data Overrun ...
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Register Description 7.15 OUTY_L (2Ah) YD7, YD0 Y axis acceleration data LSB In Big Endian Mode (bit BLE CTRL_REG2 set to ‘1’) the content of this register is the MSB acceleration data and depends by bit DAS in CTR_REG2 ...
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LIS3LV02DQ 7.19 FF_WU_CFG (30h) And/Or combination of Interrupt events interrupt request. Default value: 0. AOI (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch interrupt request. Default value: 0. LIR (0: interrupt request not latched; 1: ...
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Register Description 7.20 FF_WU_SRC (31h) Interrupt Active. Default value (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Z High. Default value (0: no interrupt event has ...
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LIS3LV02DQ 7.22 FF_WU_THS_L (34h) THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0 THS7, THS0 Free-fall / Inertial Wake Up Acceleration Threshold LSB 7.23 FF_WU_THS_H (35h) THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS15, THS8 Free-fall / Inertial Wake Up Acceleration ...
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Register Description 7.25 DD_CFG (38h) IEND Interrupt enable on Direction change. Default value: 0 IEND (0: disabled; 1: interrupt signal enabled) Latch Interrupt request into DD_SRC reg with the DD_SRC reg cleared by reading DD_ACK reg. Default value: 0. ...
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LIS3LV02DQ 7.26 DD_SRC (39h) X Interrupt event from direction change. IA (0: no direction changes detected; 1: direction has changed from previous measurement) Z High. Default value (0: Z below THSI threshold accel. exceeding THSE threshold ...
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Register Description 7.28 DD_THSI_L (3Ch) THSI7 THSI7, THSI0 Direction detection Internal Threshold LSB 7.29 DD_THSI_H (3Dh) THSI15 THSI14 THSI13 THSI15, THSI8 Direction detection Internal Threshold MSB 7.30 DD_THSE_L (3Eh) THSE7 THSE7, THSE0 7.31 DD_THSE_H (3Fh) THSE15 THSE14 THSE13 THSE12 ...
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LIS3LV02DQ 8 Typical performance characteristics 8.1 Mechanical Characteristics at 25°C Figure 10. x-axis 0-g level at 2. −10 −5 0 0−g LEVEL (mg) Figure 12. z-axis 0-g level at ...
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Typical performance characteristics 8.2 Mechanical Characteristics derived from measurement in the -40°C to +85°C temperature range Figure 16. x-axis 0-g level change vs. temperature at 2. −0.5 0 0−g level drift (mg/ Figure ...
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LIS3LV02DQ 8.3 Electro-Mechanical characteristics at 25°C Figure 22. x and y axis 0-g level as function of supply voltage −20 −40 −60 −80 2 2.2 2.4 2.6 2.8 3 Supply Voltage (V) Figure 24. Current ...
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Package Information 9 Package Information In order to meet environmental requirements, ST offers these devices in ECOPACK These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...
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LIS3LV02DQ 10 Revision history Date Revision 7-Oct-2005 1 Initial release. CD00047926 10 Revision history Changes 41/42 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...