Si4731-A-EVB Silicon Laboratories Inc, Si4731-A-EVB Datasheet - Page 19

• Manufacturer Part Number: Si4731-A-EVB
• Description: WiFi / 802.11 Modules & Development Tools Si4731 Eval Board
• Manufacturer: Silicon Laboratories Inc

Specifications of Si4731-A-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.14. GPO Outputs”. In any bus
mode, commands may only be sent after VIO and VDD
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
4.13.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
2-wire bus mode uses only the SCLK and SDIO pins for
signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a seven bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4730/31 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
Although the Si4730/31 will respond to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). When SEN = 0, the seven-bit device
address is 0010001b. When SEN = 1, the address is
1100011b.
For write operations, the user then sends an eight bit
data byte on SDIO, which is captured by the device on
rising edges of SCLK. The Si4730/31 acknowledges
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to 8
data bytes in a single 2-wire transaction. The first byte is
a command, and the next seven bytes are arguments.
For
acknowledged the control byte, it will drive an eight bit
data byte on SDIO, changing the state of SDIO on the
falling edge of SCLK. The user acknowledges each data
byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. If a data byte is not
Table 11. Bus Mode Select on Rising Edge of
Bus Mode
2-Wire
3-Wire
read
SPI
operations,
0 (must drive)
GPO1
RST
after
1
1
the
Si4730/31
1 (must drive)
GPO2
0
0
has
Rev. 1.0
acknowledged, the transaction will end. The user may
read up to 16 data bytes in a single 2-wire transaction.
These bytes contain the response data from the
Si4730/31.
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to Table 5, “2-Wire Control Interface Characteristics” on
page 7, Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8 and Figure 3, “2-
Wire Control Interface Read and Write Timing Diagram,”
on page 8.
4.13.2. 3-Wire Control Interface Mode
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
3-wire bus mode uses the SCLK, SDIO and SEN_ pins.
A transaction begins when the user drives SEN low.
Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a three-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a five-bit register address (A4:A0).
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4730/31 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9, Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
4.13.3. SPI Control Interface Mode
When selecting SPI mode, the user must ensure that a
rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
SPI bus mode uses the SCLK, SDIO and SEN pins for
read/write operations. The system controller can
choose to receive read data from the device on either
Si4730/31-A10
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