Si4731-A-EVB Silicon Laboratories Inc, Si4731-A-EVB Datasheet - Page 7

• Manufacturer Part Number: Si4731-A-EVB
• Description: WiFi / 802.11 Modules & Development Tools Si4731 Eval Board
• Manufacturer: Silicon Laboratories Inc

Specifications of Si4731-A-EVB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. 2-Wire Control Interface Characteristics
(V
Parameter
SCLK Frequency
SCLK Low Time
SCLK High Time
SCLK Input to SDIO
(START)
SCLK Input to SDIO
(START)
SDIO Input to SCLK
SDIO Input to SCLK
SCLK input to SDIO
(STOP)
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
DD
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
4. The Si4730/31 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the 0 ns t
5. The maximum t
= 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, T
high) does not occur within 300 ns before the rising edge of RST.
until after the 1st start condition.
specification.
violated so long as all other timing parameters are met.
HD:DAT
↑
↓
↓
↑
↓
Setup
Setup
Hold
Setup
Hold
has only to be met when f
4,5
A
= –20 to 85 °C)
Symbol
t
t
t
t
t
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
t
f
t
f:OUT
HIGH
t
LOW
t
BUF
t
SCL
C
f:IN
r:IN
SP
b
SCL
Test Condition
Rev. 1.0
= 400 kHz. At frequencies below 400 KHz, t
1,2,3
20 + 0.1 x C
20 + 0.1 x C
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
—
—
0
0
b
b
Si4730/31-A10
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
HD:DAT
Max
400
900
250
300
50
50
—
—
—
—
—
—
—
may be
HD:DAT
Unit
kHz
pF
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
7