5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 16
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5M80ZT100C5N
Manufacturer Part Number
5M80ZT100C5N
Description
ALTERA
Manufacturer
Altera
Series
MAX Vr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(164 pages)
3.DK-DSP-3SL150N.pdf
(80 pages)
4.5M80ZT100C5N.pdf
(72 pages)
Specifications of 5M80ZT100C5N
Cpld Type
FLASH
No. Of Macrocells
64
No. Of I/o's
79
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
118.3MHz
Supply Voltage Range
1.71V To 1.89V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
80
Number Of Macrocells
64
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M80ZT100C5N
Manufacturer:
ALTERA
Quantity:
825
Part Number:
5M80ZT100C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
3–16
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 2 of 3)
MAX V Device Handbook
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DSS
DSH
DDS
DDH
DP
PB
BP
PPMX
AE
EB
BE
EPMX
DCO
OE
Symbol
Data register shift signal
setup to data register
clock
Data register shift signal
hold from data register
clock
Data register data in
setup to data register
clock
Data register data in hold
from data register clock
Program signal to data
clock hold time
Maximum delay between
program rising edge to
UFM busy signal rising
edge
Minimum delay allowed
from UFM busy signal
going low to program
signal going low
Maximum length of busy
pulse during a program
Minimum erase signal
to address clock hold
time
Maximum delay between
the erase rising edge to
the UFM busy signal
rising edge
Minimum delay allowed
from the UFM busy
signal going low to
erase signal going low
Maximum length of busy
pulse during an erase
Delay from data register
clock to data register
output
Delay from OSC_ENA
signal reaching UFM to
rising clock of OSC
leaving the UFM
Parameter
Min
180
60
20
20
20
—
20
—
—
20
—
—
0
0
5M40Z/ 5M80Z/ 5M160Z/
C4
5M240Z/ 5M570Z
Max
960
100
960
500
—
—
—
—
—
—
—
—
—
5
Min
180
60
20
20
20
—
20
—
—
20
—
—
0
0
C5, I5
Chapter 3: DC and Switching Characteristics for MAX V Devices
Max
960
100
960
500
—
—
—
—
—
—
—
—
—
5
Min
180
60
20
20
20
—
20
—
—
20
—
—
0
0
C4
5M1270Z/ 5M2210Z
Max
960
100
960
500
—
—
—
—
—
—
—
—
—
5
January 2011 Altera Corporation
Timing Model and Specifications
Min
180
60
20
20
20
—
20
—
—
20
—
—
0
0
C5, I5
Max
960
100
960
500
—
—
—
—
—
—
—
—
—
5
Unit
ms
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns