24LC04BHT-E/ST Microchip Technology, 24LC04BHT-E/ST Datasheet - Page 5

• Manufacturer Part Number: 24LC04BHT-E/ST
• Description: 4K, 512 X 8 2.5V SERIAL EE, EXT, 1/2 ARRAY WP 8 TSSOP 4.4mm T/R
• Manufacturer: Microchip Technology

Specifications of 24LC04BHT-E/ST

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (2 x 256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.0
The 24XX04H supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX04H works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Both data and clock lines remain high.
3.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1:
© 2008 Microchip Technology Inc.
SDA
SCL
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
(A)
FUNCTIONAL DESCRIPTION
BUS CHARACTERISTICS
Bus Not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
Condition
Start
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Acknowledge
Address or
Valid
(D)
to Change
Allowed
Data
3.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out (FIFO) fashion.
3.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX04H) will leave the data
line high to enable the master to generate the Stop
condition.
24AA04H/24LC04BH
Note:
Data Valid (D)
Acknowledge
The 24XX04H does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
(D)
DS22119A-page 5
Condition
Stop
(C)
(A)