25LC1024T-I/SM Microchip Technology, 25LC1024T-I/SM Datasheet - Page 14

• Manufacturer Part Number: 25LC1024T-I/SM
• Description: IC,SERIAL EEPROM,NOR FLASH,128KX8,CMOS,SOP,8PIN,PLASTIC
• Manufacturer: Microchip Technology

Specifications of 25LC1024T-I/SM

• Rohs Compliant: YES
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1M (128K x 8)
• Speed: 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 25LC1024T-I/SMTR

25LC1024
2.8
The Page Erase function will erase all bits (FFh) inside
the given page. A Write Enable (WREN) instruction
must be given prior to attempting a Page Erase. This
is done by setting CS low and then clocking out the
proper instruction into the 25LC1024. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The Page Erase function is entered by driving CS low,
followed by the instruction code (Figure 2-8), and
three address bytes. Any address inside the page to
be erased is a valid address.
FIGURE 2-8:
DS22064D-page 14
PAGE ERASE
SCK
SO
CS
SI
PAGE ERASE SEQUENCE
0
0
1
1
0
Instruction
2
0
3
0
4
0
5
High-Impedance
1
6
0
7
23 22 21 20
8
9 10 11
CS must then be driven high after the last bit if the
address or the Page Erase will not execute. Once the
CS is driven high, the self-timed Page Erase cycle is
started. The WIP bit in the STATUS register can be
read to determine when the Page Erase cycle is
complete.
If a Page Erase function is given to an address that
has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
24-bit Address
29 30 31
2
1
 2010 Microchip Technology Inc.
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