5M1270ZF256I5N Altera, 5M1270ZF256I5N Datasheet - Page 14
5M1270ZF256I5N
Manufacturer Part Number
5M1270ZF256I5N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Specifications of 5M1270ZF256I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of Gates
-
Number Of I /o
211
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M1270ZF256I5N
Manufacturer:
ALTERA12
Quantity:
813
2–2
Figure 2–1. Device Block Diagram
MAX V Device Handbook
f
MultiTrack
Interconnect
IOE
IOE
IOE
IOE
Figure 2–1
Each MAX V device contains a flash memory block within its floorplan. This block is
located on the left side of the 5M40Z, 5M80Z, 5M160Z, and 5M240Z devices. On the
5M240Z (T144 package), 5M570Z, 5M1270Z, and 5M2210Z devices, the flash memory
block is located on the bottom-left area of the device. The majority of this flash
memory storage is partitioned as the dedicated configuration flash memory (CFM)
block. The CFM block provides the non-volatile storage for all of the SRAM
configuration information. The CFM automatically downloads and configures the
logic and I/O at power-up, providing instant-on operation.
For more information about configuration upon power-up, refer to the
and Power-On Reset for MAX V Devices
A portion of the flash memory within the MAX V device is partitioned into a small
block for user data. This user flash memory (UFM) block provides 8,192 bits of
general-purpose user storage. The UFM provides programmable port connections to
the logic array for reading and writing. There are three LAB rows adjacent to this
block, with column numbers varying by device.
IOE
shows a functional block diagram of the MAX V device.
Element
Element
Element
Element
Logic
Logic
Logic
Logic
IOE
Interconnect
MultiTrack
IOE
Element
Element
Element
Element
Logic
Logic
Logic
Logic
IOE
chapter.
IOE
Element
Element
Element
Element
Logic
Logic
Logic
Logic
IOE
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
Logic Array
BLock (LAB)
Functional Description
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