5M1270ZF256I5N Altera, 5M1270ZF256I5N Datasheet - Page 16
5M1270ZF256I5N
Manufacturer Part Number
5M1270ZF256I5N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Specifications of 5M1270ZF256I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of Gates
-
Number Of I /o
211
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
Available stocks
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Part Number
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Quantity
Price
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5M1270ZF256I5N
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ALTERA12
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2–4
Figure 2–2. Device Floorplan for MAX V Devices
Note to
(1) The device shown is a 5M570Z device. 5M1270Z and 5M2210Z devices have a similar floorplan with more LABs. For 5M40Z, 5M80Z, 5M160Z,
Logic Array Blocks
MAX V Device Handbook
and 5M240Z devices, the CFM and UFM blocks are located on the left side of the device.
Figure
Logic Array
I/O Blocks
I/O Blocks
I/O Blocks
2 GCLK
2–2:
Inputs
Blocks
Figure 2–2
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect,
a look-up table (LUT) chain, and register chain connection lines. There are 26 possible
unique inputs into an LAB, with an additional 10 local feedback input lines fed by LE
outputs in the same LAB. The local interconnect transfers signals between LEs in the
same LAB. LUT chain connections transfer the LUT output from one LE to the
shows a floorplan of a MAX V device.
(Note 1)
CFM Block
UFM Block
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
2 GCLK
Inputs
Logic Array
Blocks
Logic Array Blocks
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