AD1833AASTZ Analog Devices Inc, AD1833AASTZ Datasheet - Page 3

• Manufacturer Part Number: AD1833AASTZ
• Description: 6 Channel 24 Bit 192 KHz DAC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD1833AASTZ

• Number Of Bits: 24
• Data Interface: DSP, I²S, Serial
• Number Of Converters: 6
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
DIGITAL I/O
POWER SUPPLIES
Specifications subject to change without notice.
DIGITAL TIMING
Parameter
MASTER CLOCK AND RESET
SPI PORT
DAC SERIAL PORT
TDM MODE MASTER
TDM MODE SLAVE
AUXILIARY INTERFACE
*MCLK symmetry must be better than 60:40 or 40:60.
Specifications subject to change without notice.
REV. 0
Input Voltage HI
Input Voltage LO
Output Voltage HI
Output Voltage LO
Supply Voltage (AV
Supply Voltage (DV
Supply Current I
Supply Current I
Power Supply Rejection Ratio
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
ML
MH
PDR
CCH
CCL
CCP
CDS
CDH
CLS
CLH
DBH
DBL
DLS
DLH
DDS
DDH
TMBD
TMFSD
TMDDS
TMDDH
TSB
TSBCH
TSBCL
TSFS
TSFH
TSDDS
TSDDH
AXLRD
AXDD
AXBD
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
MCLK LO (All Modes)*
MCLK HI (All Modes)*
PD/RST LO
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CCLK Period
CDATA Setup Time
CDATA Hold Time
CLATCH Setup
CLATCH Hold
BCLK HI
BCLK LO
L/RCLK Setup
L/RCLK Hold
SDATA Setup
SDATA Hold
BCLKTDM Delay
FSTDM Delay
SDIN1 Setup
SDIN1 Hold
BCLKTDM Frequency
BCLKTDM High
BCLKTDM Low
FSTDM Setup
FSTDM Hold
SDIN1 Setup
SDIN1 Hold
L/RCLK Delay
Data Delay
AUXBCLK Delay
ANALOG
DIGITAL
DD
DD2
(Guaranteed over –40 C to +85 C, AV
and DV
)
DD1
)
2.4
DV
4.5
3.3
Min
Min
15
15
20
20
20
80
10
10
10
10
15
15
10
10
10
15
15
15
256
20
20
10
10
15
15
DD
DD2
= DV
– 0.4
f
S
–3–
DD
5
38.5
42
2
–60
–50
= 5 V
Typ
Max
20
10
10
10
20
10%)
Max
5.5
DV
42
48
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8
0.4
DD1
Unit
V
V
V
V
V
V
mA
mA
mA
dB
dB
Comments
24 MHz clock, clock doubler bypassed
24 MHz clock, clock doubler bypassed
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
To BCLK rising
From BCLK rising
To BCLK rising
From BCLK rising
From MCLK rising
From BCLKTDM rising
To BCLKTDM falling
From BCLKTDM falling
To BCLKTDM falling
From BCLKTDM falling
To BCLKTDM falling
From BCLKTDM falling
From BCLK falling
From BCLK falling
From MCLK rising
Active
Power-Down
Test Conditions
AD1833A