AD5206BRUZ100 Analog Devices Inc, AD5206BRUZ100 Datasheet - Page 18

• Manufacturer Part Number: AD5206BRUZ100
• Description: IC,Digital Potentiometer,CMOS,TSSOP,24PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD5206BRUZ100

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 6
• Temperature Coefficient: 700 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 100K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5204/AD5206
ORDERING GUIDE
Model
AD5204BN10
AD5204BR10
AD5204BR10-REEL
AD5204BRZ10
AD5204BRZ10-REEL
AD5204BRU10
AD5204BRU10-REEL7
AD5204BRUZ10
AD5204BRUZ10-REEL7
AD5204BCPZ10-REEL
AD5204BCPZ10-REEL7
AD5204BN50
AD5204BR50
AD5204BR50-REEL
AD5204BRZ50
1, 2
INDICATOR
1.00
0.85
0.80
10
10
10
10
10
10
10
10
10
10
10
50
50
50
50
kΩ
PIN 1
12° MAX
SEATING
PLANE
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
0.15
0.05
PIN 1
BSC SQ
0.10 COPLANARITY
VIEW
TOP
5.00
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Figure 37. 24-Lead Thin Shrink Small Outline Package [TSSOP]
24
1
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-153-AD
BSC
0.65
5 mm × 5 mm Body, Very Thin Quad
0.30
0.19
7.90
7.80
7.70
Dimensions shown in millimeters
BSC SQ
Dimensions shown in millimeters
4.75
0.20 REF
Rev. C | Page 18 of 20
Package Description
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Frame Chip Scale Package [LFCSP_VQ]
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
0.05 MAX
0.02 NOM
COPLANARITY
(CP-32-3)
SEATING
PLANE
(RU-24)
13
12
MAX
1.20
0.08
0.60 MAX
4.50
4.40
4.30
BSC
0.50
0.40
0.30
0.50
0.20
0.09
6.40 BSC
24
17
16
25
(BOTTOM VIEW)
0.60 MAX
8°
0°
EXPOSED
3.50 REF
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.75
0.60
0.45
32
9
1
8
3.45
3.30 SQ
3.15
0.25 MIN
PIN 1
INDICATOR
Package Option
N-24-1
RW-24
RW-24
RW-24
RW-24
RU-24
RU-24
RU-24
RU-24
CP-32-3
CP-32-3
N-24-1
RW-24
RW-24
RW-24