AD5552BRZ Analog Devices Inc, AD5552BRZ Datasheet - Page 4

no-image

AD5552BRZ

Manufacturer Part Number
AD5552BRZ
Description
14-Bit BiPolar V-Out DAC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5552BRZ

Settling Time
1µs
Number Of Bits
14
Data Interface
Serial
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
6.05mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5552BRZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD5551/AD5552
TIMING CHARACTERISTICS
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
Guaranteed by design, not production tested.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of +3 V and timed from a voltage level of +1.6 V).
DD
= 2.7 V to 5.5 V, 2.5 V ≤ V
1, 2
LDAC*
SCLK
DIN
CS
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
Limit at T
All Versions
25
40
20
20
15
15
35
20
15
0
30
30
30
t
12
REF
MIN
t
6
, T
≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ T
t
DB13
4
t
MAX
8
t
9
t
2
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Figure 3. Timing Diagram
Rev. A | Page 4 of 16
t
1
t
3
DB0
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
t
7
t
t
5
11
t
10
A
≤ +85°C, unless otherwise noted.

Related parts for AD5552BRZ