AD5662BRJ-2500RL7 Analog Devices Inc, AD5662BRJ-2500RL7 Datasheet - Page 7

• Manufacturer Part Number: AD5662BRJ-2500RL7
• Description: IC,D/A CONVERTER,SINGLE,16-BIT,CMOS,TSSOP,8PIN
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5662BRJ-2500RL7

• Design Resources: 4 mA to 20 mA Process Control Loop Using AD5662 (CN0009) 16-Bit Fully Isolated Voltage Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0063) 16-Bit Fully Isolated 4 mA to 20 mA Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0064)
• Settling Time: 8µs
• Number Of Bits: 16
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 750µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTION
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
V
V
V
V
SYNC
SCLK
DIN
GND
DD
REF
FB
OUT
Function
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. V
Reference Voltage Input.
Feedback Connection for the Output Amplifier. V
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Ground Reference Point for All Circuitry on the Part.
V
V
V
V
OUT
REF
DD
FB
Figure 3. Pin Configuration
1
2
3
4
th
Rev. A | Page 7 of 24
(Not to Scale)
clock cycle unless SYNC is taken high before this edge, in which case the
AD5662
TOP VIEW
FB
8
7
6
5
should be connected to V
GND
DIN
SCLK
SYNC
DD
should be decoupled to GND.
OUT
for normal operation.
AD5662