AD7147ACPZ-1REEL Analog Devices Inc, AD7147ACPZ-1REEL Datasheet - Page 30

• Manufacturer Part Number: AD7147ACPZ-1REEL
• Description: IC,Converter, Other/Special/Miscellaneous,LLCC,24PIN
• Manufacturer: Analog Devices Inc
• Series: CapTouch™r
• Type: Capacitive Sensor Controllerr

Specifications of AD7147ACPZ-1REEL

• Resolution (bits): 16 b
• Data Interface: I²C, Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2.6 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7147EBZ - BOARD EVAL FOR AD7147ACPZEVAL-AD7147-1EBZ - BOARD EVAL FOR AD7147ACPZ-1
• Sampling Rate (per Second): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7147
GPIO INT OUTPUT CONTROL
The INT output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is con-figured as
an input by setting the GPIO_SETUP bits in the interrupt con-
figuration register to 01. See the
(GPIO)
Enable the GPIO interrupt by setting the GPIO_INT_ENABLE
bit in Register 0x007 to 1, or disable the GPIO interrupt by
clearing this bit to 0. The GPIO status bit in the conversion-
complete interrupt status register reflects the status of the GPIO
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
READBACK
1
OUTPUT
OUTPUT
READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
SERIAL
INPUT
INPUT
Figure 43. Example of INT Output Controlled by the GPIO Input
GPIO
GPIO
INT
INT
section for more information on configuring the GPIO.
(GP IO_SETUP = 01, GPIO_INPUT_CONFIG = 00)
General-Purpose Input/Output
1
Rev. B | Page 30 of 72
interrupt. This bit is set to 1 when the GPIO has triggered INT .
The bit is cleared upon reading the GPIO_INT_STATUS bit if the
condition that caused the interrupt is no longer present.
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 15 shows
how the settings of the GPIO_INPUT_CONFIG bits in the inter-
rupt enable (STAGE_LOW_INT_ENABLE) register affect the
behavior of INT .
Figure 43 to Figure 46 show how the interrupt output is cleared
upon a read from the GPIO_INT_STATUS bit.
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
READBACK
1
OUTPUT
OUTPUT
READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
SERIAL
INPUT
INPUT
Figure 44. Example of INT Output Controlled by the GPIO Input
GPIO
GPIO
INT
INT
(GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01)
1