AD73360ASUZ Analog Devices Inc, AD73360ASUZ Datasheet - Page 6
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AD73360ASUZ
Manufacturer Part Number
AD73360ASUZ
Description
6-CHANNEL SIGMA-DELTA ADC I.C.
Manufacturer
Analog Devices Inc
Datasheet
1.AD73360LARZ-REEL.pdf
(35 pages)
Specifications of AD73360ASUZ
Number Of Bits
16
Number Of Channels
6
Power (watts)
80mW
Voltage - Supply, Analog
2.7 V ~ 3.3 V
Voltage - Supply, Digital
2.7 V ~ 3.3 V
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD73360LEB - BOARD EVAL FOR AD73360L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD73360ASUZ
Manufacturer:
ADI
Quantity:
219
Company:
Part Number:
AD73360ASUZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
AD73360ASUZ-REEL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD73360
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
10
11
12
13
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
1
1
A
A
= –40 C to +85 C
= –40 C to +85 C
1
1
1
1
(AVDD = 5 V
noted)
(AVDD = 3 V
noted)
10%; DVDD = 5 V
10%; DVDD = 3 V
–6–
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
10%; AGND = DGND = 0 V; T
10%; AGND = DGND = 0 V; T
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
A
A
= T
= T
MlN
MlN
to T
to T
MAX
MAX
, unless otherwise
, unless otherwise
REV. A