AD7356BRUZ Analog Devices Inc, AD7356BRUZ Datasheet - Page 10

• Manufacturer Part Number: AD7356BRUZ
• Description: 12-Bit Dual Diff Simult 5 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7356BRUZ

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041)
• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 59mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7356
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (1 LSB below
the first code transition) and full scale (1 LSB above the last
code transition).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Negative Full-Scale Error
Negative full-scale error is the deviation of the first code
transition (00 … 000) to (00 … 001) from the ideal (that is,
−V
Negative Full-Scale Error Match
Negative full-scale error match is the difference in negative full-
scale error between the two ADCs.
Midscale Error
Midscale error is the deviation of the midscale code transition
(011 … 111) to (100 … 000) from the ideal (that is, 0 V).
Midscale Error Match
Midscale error match is the difference in midscale error
between the two ADCs.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code
transition (111 … 110) to (111 … 111) from the ideal (that is,
V
Positive Full-Scale Error Match
Positive full-scale error match is the difference in positive full-
scale error between the two ADCs.
ADC-to-ADC Isolation
ADC-to-ADC isolation is a measure of the level of crosstalk
between ADC A and ADC B. It is measured by applying a full-
scale 1 MHz sine wave signal to one of the two ADCs and
applying a full-scale signal of variable frequency to the other
ADC. The ADC-to-ADC isolation is defined as the ratio of the
power of the 1 MHz signal on the converted ADC to the power
of the noise signal on the other ADC that appears in the FFT.
The noise frequency on the unselected channel varies from
100 kHz to 2.5 MHz.
REF
REF
− 1.5 LSB) after the midscale error has been adjusted out.
+ 0.5 LSB) after the midscale error has been adjusted out.
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Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC V
of the input varies from 5 kHz to 25 MHz.
where:
Pf is the power at frequency, f, in the ADC output.
Pf
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV p-p sine
wave applied to the common-mode voltage of V
of frequency, f
where:
Pf is the power at frequency (f) in the ADC output.
Pf
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±0.5 LSB, after the end of a conversion.
Signal-to-(Noise and Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal-to-(noise and distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical SINAD for an ideal N-bit converter with a sine
wave input is given by
Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit
converter, SINAD is 86 dB.
S
S
is the power at frequency, f
is the power at frequency (f
PSRR (dB) = 10 log(Pf/Pf
CMRR (dB) = 10 log(Pf/Pf
SINAD = (6.02 N + 1.76) dB
S
.
DD
supply of frequency, f
S
S
)
S
, in the ADC output.
S
) in the ADC output.
)
S
/2), excluding dc. The ratio is
S
. The frequency
IN+
and V
IN−