AD7357BRUZ-RL Analog Devices Inc, AD7357BRUZ-RL Datasheet - Page 5
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AD7357BRUZ-RL
Manufacturer Part Number
AD7357BRUZ-RL
Description
14-Bit Dual Diff Simult 5 MSPS ADC I.C.
Manufacturer
Analog Devices Inc
Datasheet
1.AD7357BRUZ.pdf
(20 pages)
Specifications of AD7357BRUZ-RL
Design Resources
DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
Number Of Bits
14
Sampling Rate (per Second)
4.2M
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
59mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP (0.173", 4.40mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD7357BRUZ-RL
Manufacturer:
ADI
Quantity:
1 000
TIMING SPECIFICATIONS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
Latency
1
2
3
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
Temperature ranges are as follows: AD7357Y: −40°C to +125°C, AD7357B: −40°C to +85°C, AD7357WY: −40°C to +125°C.
Specified with a load capacitance of 10 pF on SDATA
The time required for the output to cross 0.4 V or 2.4 V.
2, 3
2
2
DD
2
= 2.5 V ± 10%, V
Limit at T
500
80
t
5
5
6
12.5
11
9.5
9
5
5
3.5
3
9.5
5
4.5
9.5
2
+ 15.5 × t
DRIVE
= 2.25 V to 3.6 V, internal reference = 2.048 V, T
MIN
SCLK
1 conversion latency
, T
MAX
Unit
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
A
and SDATA
B
.
Rev. A | Page 5 of 20
Description
t
Minimum time between end of serial read and next falling edge of CS
CS to SCLK setup time
Delay from CS until SDATA
Data access time after SCLK falling edge
1.8 V ≤ V
2.25 V ≤ V
2.75 V ≤ V
3.3 V ≤ V
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
1.8 V ≤ V
2.75 V ≤ V
CS rising edge to SDATA , SDATA
CS rising edge to falling edge pulse width
SCLK falling edge to SDATA
SCLK falling edge to SDATA
SCLK
= 1/f
DRIVE
DRIVE
DRIVE
SCLK
DRIVE
DRIVE
DRIVE
A
< 2.25 V
≤ 3.6 V
< 2.75 V
= T
< 2.75 V
< 3.3 V
≤ 3.6 V
MAX
to T
A
MIN
A
A
A
and SDATA
1
, SDATA
, SDATA
, unless otherwise noted.
B
, high impedance
B
B
, high impedance
, high impedance
B
are three-state disabled
AD7357