AD7394ARZ Analog Devices Inc, AD7394ARZ Datasheet - Page 6

• Manufacturer Part Number: AD7394ARZ
• Description: X2, 12-Bit, +3V UPwr DAC
• Manufacturer: Analog Devices Inc

Specifications of AD7394ARZ

• Settling Time: 60µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Channels: 2
• Resolution: 12b
• Conversion Rate: 17KSPS
• Interface Type: Serial (3-Wire)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±2LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD7394
Table 2. Control Logic Truth Table
CS
H
L
L
L
L
L
↑+
H
H
X
X
X
X
X
1
2
Table 3. AD7394 Serial Input Register Data Format, Data Is Loaded in MSB-First Format
MSB
B11
D11
↑+ positive logic transition; ￬− negative logic transition; X don’t care.
Do not clock in serial data while level sensitive inputs LDA or LDB are logic low.
1
CLK
X
L
H
↑+
↑+
H
L
X
X
X
X
X
X
X
RS
H
H
H
H
H
H
H
H
H
L
↑+
L
↑+
X
B10
D10
MSB
X
X
X
X
X
X
X
X
X
H
H
L
L
X
SHDN
H
H
H
H
H
H
H
H
H
H
H
H
H
L
B9
D9
L
X
LDA/LDB
H
H
H
H
L
H
￬−
L
X
H
H
X
2
B8
D8
Serial Shift Register Function
No effect
No effect
No effect
Shift-register-data advanced one bit
Shift-register-data advanced one bit
No effect
No effect
No effect
No effect
No effect
No effect
No effect
No effect
No effect
B7
D7
Rev. A | Page 6 of 16
B6
D6
B5
D5
B4
D4
DAC Register Function
Latched
Latched
Latched
Latched
Transparent
Transparent
Latched
Updated with current shift register contents
Transparent
Loaded with 800
Latched with 800
Loaded with all zeros
Latched all zeros
No affect
B3
D3
B2
D2
H
H
B1
D1
LSB
B0
D0