AD7476SRTZ-R2 Analog Devices Inc, AD7476SRTZ-R2 Datasheet - Page 16

• Manufacturer Part Number: AD7476SRTZ-R2
• Description: IC,A/D CONVERTER,SINGLE,12-BIT,TSOP,6PIN
• Manufacturer: Analog Devices Inc

Specifications of AD7476SRTZ-R2

• Design Resources: Output Channel Monitoring Using AD5380 (CN0008) AD5382 Channel Monitor Function (CN0012) AD5381 Channel Monitor Function (CN0013) AD5383 Channel Monitor Function (CN0015) AD5390/91/92 Channel Monitor Function (CN0030) Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 17.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7476ACBZ - BOARD EVALUATION FOR AD7476AAD7476-DBRD - BOARD EVAL FOR AD7476AD7476A-DBRD - BOARD EVAL FOR AD7476A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7476/AD7477/AD7478
Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered
between each conversion, or a series of conversions can be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7476/AD7477/
AD7478 is in power-down mode, all analog circuitry is
powered down.
To enter power-down, the conversion process must be
interrupted by bringing CS high any time after the second
falling edge of SCLK and before the tenth falling edge of SCLK,
as shown in Figure 20. Once CS is brought high in this window
of SCLKs, the part enters power-down and the conversion
initiated by the falling edge of CS is terminated and SDATA
goes back into three-state.
SDATA
SCLK
CS
A
1
THE PART BEGINS
TO POWER UP
SDATA
SDATA
SCLK
SCLK
CS
CS
INVALID DATA
10
1
1
2
Figure 20. Entering Power-Down Mode
Figure 21. Exiting Power-Down Mode
4 LEADING ZEROS + CONVERSION RESULT
Figure 19. Normal Mode Operation
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If CS is brought high before the second SCLK falling edge, the
part remains in normal mode and does not power down. This
avoids accidental power-down due to glitches on the CS line.
To exit this mode of operation and power up the AD7476/
AD7477/AD7478 again, perform a dummy conversion. On the
falling edge of CS , the device begins to power up, and continues
to power up as long as CS is held low until after the falling edge
of the tenth SCLK. The device is fully powered up once 16
SCLKs have elapsed and, as shown in Figure 21, valid data
results from the next conversion. If CS is brought high before
the tenth falling edge of SCLK, the AD7476/AD7477/AD7478
again goes back into power-down. This avoids accidental
power-up due to glitches on the CS line or an inadvertent burst
of eight SCLK cycles while CS is low. Although the device may
begin to power up on the falling edge of CS , it powers down
again on the rising edge of CS as long as it occurs before the
tenth SCLK falling edge.
10
THREE-STATE
10
1
THE PART IS FULLY POWERED
UP WITH V
IN
FULLY ACQUIRED
16
16
VALID DATA
16