AD7631BCPZ Analog Devices Inc, AD7631BCPZ Datasheet - Page 10

• Manufacturer Part Number: AD7631BCPZ
• Description: IC,A/D CONVERTER,SINGLE,18-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7631BCPZ

• Number Of Bits: 18
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 120mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7631
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Mnemonic
D12 or
SYNC
D13 or
RDERROR
D14 or
HW/SW
D15 or
SCIN
D16 or
SCCLK
D17 or
SCCS
BUSY
TEN
RD
CS
RESET
PD
CNVST
BIPOLAR
Type
DO
DO
DI/O
DI/O
DI/O
DI/O
DO
DI
DI
DI
DI
DI
DI
DI
2
2
2
1
Description
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Frame Synchronization. In serial master mode (MODE[1:0] = 3,
EXT/INT= low), this output is used as a digital output frame synchronization for use with the
internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while
the SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
the SDOUT output is valid.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Data Read Error. In serial slave mode (MODE[1:0] = 3, EXT/INT = high),
this output is used as an incomplete data read error flag. If a data read is started and not completed when
the current conversion is completed, the current data is lost and RDERROR is pulsed high.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Hardware/Software Select. In serial mode, this input is
used to configure the AD7631 by hardware or software. See the Hardware Configuration section and
Software Configuration section.
When HW/SW = low, the AD7631 is configured through software using the serial configuration register.
When HW/SW = high, the AD7631 is configured through dedicated hardware input pins.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Data Input. In serial software configuration mode (HW/SW =
low), this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Clock. In serial software configuration mode (HW/SW = low)
this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated
depends on the logic state of the INVSCLK pin. See the
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.
When MODE[1:0] = 3, Serial Configuration Chip Select. In serial software configuration mode
(HW/SW = low), this input enables the serial configuration port. See the
Busy Output. Transitions high when a conversion is started and remains high until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
as a data-ready clock signal. Note that in master read after convert mode (MODE[1:0] = 3, EXT/INT = low,
RDC = low) the busy time changes according to
Input Range Select. Used in conjunction with BIPOLAR per the following.
Input Range (V)
0 to 5
0 to 10
±5
±10
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS
is also used to gate the external clock in slave serial mode (not used for serial configurable port).
Reset Input. When high, reset the AD7631. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register.
See the
Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Input Range Select. See description for Pin 30.
Digital Interface
BIPOLAR
High
High
Low
Low
section. If not used, this pin can be tied to OGND.
Rev. A | Page 10 of 32
TEN
Low
High
Low
High
Table 4
Software Configuration
.
Software Configuration
Software Configuration
section.
section.
section.