AD7703ANZ Analog Devices Inc, AD7703ANZ Datasheet - Page 15
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AD7703ANZ
Manufacturer Part Number
AD7703ANZ
Description
20-BIT S-D ADC IC
Manufacturer
Analog Devices Inc
Datasheet
1.AD7703AR-REEL.pdf
(16 pages)
Specifications of AD7703ANZ
Number Of Bits
20
Sampling Rate (per Second)
4k
Data Interface
Serial
Number Of Converters
1
Power Dissipation (max)
37mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Number Of Elements
1
Resolution
20Bit
Architecture
Delta-Sigma
Sample Rate
16KSPS
Input Polarity
Unipolar/Bipolar
Input Type
Voltage
Rated Input Volt
2.5/±2.5V
Differential Input
No
Power Supply Requirement
Dual
Single Supply Voltage (typ)
Not RequiredV
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (typ)
±5V
Dual Supply Voltage (min)
±4.5V
Dual Supply Voltage (max)
±5.5V
Power Dissipation
37mW
Differential Linearity Error
±0.5LSB(Typ)
Integral Nonlinearity Error
±0.003%FSR
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
20
Package Type
PDIP
Input Signal Type
Single-Ended
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Synchronous External Clock Mode (SEC)
The SEC mode (MODE pin grounded) is designed for direct
interface to the synchronous serial ports of industry-standard
microprocessors such as the 68HC11 and 68HC05. The SEC
mode also allows customized interfaces, using I/O port pins, to
microprocessors that do not have a direct fit with the AD7703’s
other mode.
As shown in Figure 17, a falling edge on CS enables the serial
data output with the MSB initially valid. Subsequent data bits
change on the falling edge of an externally supplied SCLK. After
the LSB has been transmitted, DRDY and SDATA go three-state.
If CS is low and the AD7703 is still transmitting data when a
new data-word becomes available, the old data-word continues
to be transmitted and the new data is lost.
If CS is taken high at any time during data transmission, SDATA
will go three-state immediately. If CS returns low, the AD7703
will continue transmission with the same data bit. If transmis-
sion has not been initiated and completed by the time the next
data-word becomes available, and if CS is high, DRDY returns
high for four clock cycles, then falls as the new word is loaded
into the output register.
REV. E
SDATA (O)
DRDY (O)
SCLK (O)
CS (I)
HI-Z
DB19 (MSB)
Figure 17. Timing Diagram for SEC Mode
DB18
–15–
DB17
DIGITAL NOISE AND OUTPUT LOADING
As mentioned earlier, the AD7703 divides its internal timing
into two distinct phases, analog sampling and settling and digi-
tal computation. In the SSC mode, data is transmitted only
during the digital computation periods, to minimize the effects
of digital noise on analog performance. In the SEC mode, data
transmission is externally controlled, so this automatic safeguard
does not exist. To compensate, synchronize the AD7703 to the
digital system clock via CLKIN when used in the SEC mode.
Whatever mode of operation is used, resistive and capacitive
loads on digital outputs should be minimized in order to reduce
crosstalk between analog and digital portions of the circuit. For
this reason, connection to low power CMOS logic such as one
of the 4000 series or 74C families is recommended.
DB2
DB1
DB0 (LSB)
AD7703
HI-Z