AD7706BN Analog Devices Inc, AD7706BN Datasheet - Page 12

• Manufacturer Part Number: AD7706BN
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7706BN

• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Through Hole
• Features: 3V/5V, 1mW, 3-Channel, 16-Bit Sigma Delta ADC
• No. Of Channels: 3
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD7706EBZ - BOARD EVALUATION FOR AD7706
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant

AD7705/AD7706
OUTPUT NOISE (5 V OPERATION)
Table 5 shows the AD7705/AD7706 output rms noise for the
selectable notch and −3 dB frequencies for the parts, as selected
by FS0 and FS1 of the clock register. The numbers given are for
the bipolar input ranges with a V
These numbers are typical and are generated at an analog input
voltage of 0 V with the parts used in either buffered or unbuffered
mode. Table 6 shows the output peak-to-peak noise for the
selectable notch and −3 dB frequencies for the parts.
Table 5. Output RMS Noise vs. Gain and Output Update Rate @ 5 V
Filter First
Notch and
O/P Data Rate
MCLK IN = 2.4576 MHz
50 Hz
60 Hz
250 Hz
500 Hz
MCLK IN = 1 MHz
20 Hz
25 Hz
100 Hz
200 Hz
Table 6. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V
Filter First
Notch and
O/P Data Rate
MCLK IN = 2.4576 MHz
50 Hz
60 Hz
250 Hz
500 Hz
MCLK IN = 1 MHz
20 Hz
25 Hz
100 Hz
200 Hz
−3 dB
Frequency
13.1 Hz
15.72 Hz
65.5 Hz
131 Hz
5.24 Hz
6.55 Hz
26.2 Hz
52.4 Hz
−3 dB
Frequency
13.1 Hz
15.72 Hz
65.5 Hz
131 Hz
5.24 Hz
6.55 Hz
26.2 Hz
52.4 Hz
10
4.1
5.1
Gain of 1
16
16
13
16
16
13
10
Gain of 1
110
550
4.1
5.1
110
550
REF
of 2.5 V and V
Gain of 2
16
16
13
10
16
16
13
10
Gain of 2
2.1
2.5
49
285
2.1
2.5
49
285
DD
= 5 V.
Gain of 4
16
16
13
10
16
16
13
10
Gain of 4
1.2
1.4
31
145
1.2
1.4
31
145
Rev. C | Page 12 of 44
Typical Peak-to-Peak Resolution Bits
Typical Output RMS Noise in μV
Gain of 8
16
16
13
10
16
16
13
10
Gain of 8
0.75
0.8
17
70
0.75
0.8
17
70
Note that these numbers represent the resolution for which
there is no code flicker. They are not calculated based on rms
noise, but on peak-to-peak noise. The numbers given are for
bipolar input ranges with a V
unbuffered mode. These numbers are typical and are rounded
to the nearest LSB. The numbers apply for the CLKDIV bit of
the clock register set to 0.
Gain of 16
0.7
0.75
8
41
0.7
0.75
8
41
Gain of 16
16
15
13
10
16
15
13
10
Gain of 32
Gain of 32
0.66
0.7
3.6
22
0.66
0.7
3.6
22
16
14
13
10
16
14
13
10
REF
of 2.5 V for either buffered or
Gain of 64
0.63
0.67
2.3
9.1
0.63
2.3
9.1
Gain of 64
15
14
12
10
15
14
12
10
0.67
Gain of 128
0.6
0.62
1.7
4.7
0.6
0.62
1.7
4.7
Gain of 128
14
13
12
10
14
13
12
10