AD797BRZ-REEL Analog Devices Inc, AD797BRZ-REEL Datasheet - Page 14

• Manufacturer Part Number: AD797BRZ-REEL
• Description: IC,Operational Amplifier,SINGLE,BIPOLAR,SOP,8PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD797BRZ-REEL

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Slew Rate: 20 V/µs
• Gain Bandwidth Product: 110MHz
• -3db Bandwidth: 8MHz
• Current - Input Bias: 250nA
• Voltage - Input Offset: 10µV
• Current - Supply: 8.2mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): ±5 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD797
The I-to-V converter is a special case of the follower configu-
ration. When the AD797 is used in an I-to-V converter, for
example as a DAC buffer, the circuit shown in Figure 39 should
be used. The value of C
than 33 pF, a 100 Ω series resistor is required. A bypassed balancing
resistor (R
THE INVERTING CONFIGURATION
The inverting configuration (see Figure 40) presents a low input
impedance, R1, to the source. For this reason, the goals of both
low noise and input buffering are at odds with one another.
Nonetheless, the excellent dynamics of the AD797 makes
it the preferred choice in many inverting applications, and
with careful selection of feedback resistors, the noise penalties
are minimal. Some examples are presented in Table 7 and
Figure 40.
Table 7. Values for Inverting Circuit
Gain
−1
−1
−10
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
C
S
R1
1 kΩ
300 Ω
150 Ω
S
and C
I
R1
IN
R
Figure 40. Inverting Amplifier Connection
S
Figure 39. I-to-V Converter Connection
R
20pF TO 120pF
S
) can be included to minimize dc errors.
S
2
3
R2
1 kΩ
300 Ω
1500 Ω
2
3
L
C
AD797
depends on the DAC, and if C
L
AD797
R
+V
–V
+V
–V
1
7
4
7
4
S
S
S
S
R
2
100Ω
≈ 5 pF
C
≈ 20 pF
≈ 10 pF
*
*
6
*
*
6
L
600Ω
R
Noise
(Excluding R
3.0 nV/√Hz
1.8 nV/√Hz
1.8 nV/√Hz
L
L
is greater
S
)
Rev. H | Page 14 of 20
DRIVING CAPACITIVE LOADS
The capacitive load driving capabilities of the AD797 are
displayed in Figure 41. At gains greater than 10, usually no
special precautions are necessary. If more drive is desirable,
however, the circuit shown in Figure 42 should be used. For
example, this circuit allows a 5000 pF load to be driven cleanly
at a noise gain ≥2.
SETTLING TIME
The AD797 is unique among ultralow noise amplifiers in that it
settles to 16 bits (<150 μV) in less than 800 ns. Measuring this
performance presents a challenge. A special test circuit (see
Figure 43) was developed for this purpose. The input signal was
obtained from a resonant reed switch pulse generator, available
from Tektronix as calibration Fixture No. 067-0608-00. When
open, the switch is simply 50 Ω to ground and settling is purely
a passive pulse decay and inherently flat. The low repetition rate
signal was captured on a digital oscilloscope after being
amplified and clamped twice. The selection of plug-in for the
oscilloscope was made for minimum overload recovery.
Figure 42. Recommended Circuit for Driving a High Capacitance Load
100nF
100pF
Figure 41. Capacitive Load Drive Capability vs. Closed-Loop Gain
10nF
10pF
1nF
1pF
1kΩ
*USE THE POWER SUPPLY BYPASSING SHOWN IN FIGURE 35.
1
200pF
2
3
AD797
+V
–V
20pF
7
4
1kΩ
10
S
S
CLOSED-LOOP GAIN
100Ω
*
*
6
33Ω
100
C1
1
k