AD9221AR-REEL Analog Devices Inc, AD9221AR-REEL Datasheet

no-image

AD9221AR-REEL

Manufacturer Part Number
AD9221AR-REEL
Description
IC,A/D CONVERTER,SINGLE,12-BIT,CMOS,SOP,28PIN
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9221AR-REEL

Rohs Status
RoHS non-compliant
Number Of Bits
12
Sampling Rate (per Second)
1.5M
Data Interface
Parallel
Number Of Converters
7
Power Dissipation (max)
70mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (0.300", 7.50mm Width)
For Use With
AD9221-EB - BOARD EVAL FOR AD9221
Lead Free Status / RoHS Status
GENERAL DESCRIPTION
The AD9221, AD9223, and AD9220 are a generation of high
performance, single supply 12-bit analog-to-digital converters.
Each device exhibits true 12-bit linearity and temperature drift
performance
AD9221/AD9223/AD9220 share the same interface options,
package, and pinout. Thus, the product family provides an upward
or downward component selection path based on performance,
sample rate and power. The devices differ with respect to their
specified sampling rate, and power consumption, which is reflected
in their dynamic performance over frequency.
The AD9221/AD9223/AD9220 combine a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid and monolithic implementations at
a fraction of the power consumption and cost. Each device is a
complete, monolithic ADC with an on-chip, high performance,
low noise sample-and-hold amplifier and programmable voltage
reference. An external reference can also be chosen to suit the
dc accuracy and temperature drift requirements of the application.
The devices use a multistage differential pipelined architecture
with digital output error correction logic to provide 12-bit accu-
racy at the specified data rates and to guarantee no missing
codes over the full operating temperature range.
The input of the AD9221/AD9223/AD9220 is highly flexible,
allowing for easy interfacing to imaging, communications, medi-
cal, and data-acquisition systems. A truly differential input
structure allows for both single-ended and differential input
interfaces of varying input spans. The sample-and-hold
NOTES
1
2
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Excluding internal voltage reference.
Depends on the analog input configuration.
FEATURES
Monolithic 12-Bit A/D Converter Product Family
Family Members Are: AD9221, AD9223, and AD9220
Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and
Low Power Dissipation: 59 mW, 100 mW, and 250 mW
Single 5 V Supply
Integral Nonlinearity Error: 0.5 LSB
Differential Nonlinearity Error: 0.3 LSB
Input Referred Noise: 0.09 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Signal-to-Noise and Distortion Ratio: 70 dB
Spurious-Free Dynamic Range: 86 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC and 28-Lead SSOP
10.0 MSPS
Voltage Reference
1
as well as 11.5-bit or better ac performance.
2
The
Complete 12-Bit 1.5/3.0/10.0 MSPS
amplifier (SHA) is equally suited for both multiplexed sys-
tems that switch full-scale voltage levels in successive channels
as well as sampling single-channel inputs at frequencies up to
and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220
is well suited for communication systems employing Direct-
IF down conversion since the SHA in the differential input
mode can achieve excellent dynamic performance far beyond its
specified Nyquist frequency.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over-
flow condition that can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9221/AD9223/AD9220 family offers a complete single-
chip sampling 12-bit, analog-to-digital conversion function in
pin compatible 28-lead SOIC and SSOP packages.
Flexible Sampling Rates—The AD9221, AD9223, and AD9220
offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS,
respectively.
Low Power and Single Supply—The AD9221, AD9223, and
AD9220 consume only 59 mW, 100 mW, and 250 mW, respec-
tively, on a single 5 V power supply.
Excellent DC Performance Over Temperature—The AD9221/
AD9223/AD9220 provide 12-bit linearity and temperature drift
performance.
Excellent AC Performance and Low Noise—The AD9221/
AD9223/AD9220 provide better than 11.3 ENOB performance
and have an input referred noise of 0.09 LSB rms.
Flexible Analog Input Range—The versatile on-board sample-
and-hold (SHA) can be configured for either single-ended or
differential inputs of varying input spans.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
SENSE
CAPT
CAPB
VREF
VINA
VINB
SHA
SELECT
MODE
AD9221/AD9223/AD9220
Monolithic A/D Converters
1
FUNCTIONAL BLOCK DIAGRAM
A/D
GAIN = 16
MDAC1
REFCOM
5
5
© 2003 Analog Devices, Inc. All rights reserved.
CLK
1V
DIGITAL CORRECTION LOGIC
A/D
OUTPUT BUFFERS
AD9221/AD9223/AD9220
2
GAIN = 8
MDAC2
4
AVDD
AVSS
4
12
DVSS
DVDD
A/D
GAIN = 4
MDAC3
3
3
CML
www.analog.com
2
A/D
3
OTR
BIT 1
(MSB)
BIT 12
(LSB)

Related parts for AD9221AR-REEL

AD9221AR-REEL Summary of contents

Page 1

FEATURES Monolithic 12-Bit A/D Converter Product Family Family Members Are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS Low Power Dissipation: 59 mW, 100 mW, and 250 mW Single 5 V Supply Integral Nonlinearity ...

Page 2

AD9221/AD9223/AD9220–SPECIFICATIONS (AVDD = 5 V, DVDD = SPECIFICATIONS otherwise noted.) Parameter RESOLUTION MAX CONVERSION RATE INPUT REFERRED NOISE (TYP REF V = 2.5 V REF ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ...

Page 3

V, DVDD SPECIFICATIONS Ended Input T Parameter MAX CONVERSION RATE DYNAMIC PERFORMANCE Input Test Frequency 1 (VINA = –0.5 dBFS) Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOBs) Signal-to-Noise Ratio (SNR) Total ...

Page 4

... JC +6.5 V +0.3 V AVDD + 0.3 V DVDD + 0.3 V AVDD + 0.3 V Model AVDD + 0.3 V AVDD + 0.3 V AD9221AR AVDD + 0.3 V AD9223AR °C 150 AD9220AR °C +150 AD9221ARS AD9223ARS °C 300 AD9220ARS AD9221-EB AD9223-EB AD9220-EB –4– pF) L AD9223 AD9220 Unit 333 100 ns min 150 45 ns min ...

Page 5

PIN CONFIGURATION 1 CLK 28 2 (LSB) BIT BIT 11 26 BIT AD9221/ BIT AD9223/ 6 AD9220 BIT BIT 7 22 TOP VIEW (Not to Scale) 8 BIT ...

Page 6

AD9221/AD9223/AD9220 AD9221–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4095 CODE TPC 1. Typical DNL 80 75 –0.5dB 70 –6.0dB –20.0dB 0.1 1.0 FREQUENCY – MHz TPC ...

Page 7

AD9223–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4095 CODE TPC 10. Typical DNL 80 75 –0.5dB 70 –6.0dB –20.0dB 0.1 1.0 10.0 FREQUENCY – MHz TPC ...

Page 8

AD9221/AD9223/AD9220 AD9220–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 1 4095 CODE TPC 19. Typical DNL 80 75 –0.5dB 70 –6dB –20dB 0.1 1.0 10.0 FREQUENCY – MHz ...

Page 9

INTRODUCTION The AD9221/AD9223/AD9220 are members of a high perfor- mance, complete single-supply 12-bit ADC product family based on the same CMOS pipelined architecture. The product family allows the system designer an upward or downward component selection path based on dynamic ...

Page 10

AD9221/AD9223/AD9220 The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily config- ure the inputs for either single-ended operation ...

Page 11

Referring to Figure 5, the differential SHA is implemented using a switched-capacitor topology. Therefore, its input impedance and its subsequent effects on the input drive source should be understood to maximize the converter’s performance. The com- bination of the pin ...

Page 12

AD9221/AD9223/AD9220 shunt capacitor can help limit the wideband noise at the A/D’s input by forming a low-pass filter. Note, however, that the combination of this series resistance with the equivalent input capacitance of the AD9221/AD9223/AD9220 should be evalu- ated for ...

Page 13

Input Input Connection Coupling Span (V) VINA* Single-Ended × VREF × VREF 2.5 – VREF Single-Ended × VREF × VREF 5 2 × VREF 2.5 – ...

Page 14

AD9221/AD9223/AD9220 Reference Input Span (VINA–VINB) Operating Mode (V p-p) INTERNAL 2 INTERNAL 5 2 ≤ SPAN ≤ 5 and INTERNAL SPAN = 2 × VREF 2 ≤ SPAN ≤ 5 EXTERNAL (Nondynamic) 2 ≤ SPAN ≤ 5 EXTERNAL (Dynamic) DRIVING ...

Page 15

OPTIONAL AC COUPLING AVDD V CAPACITOR 1N4148 30 D1 1N4148 V EE Figure 12. Simple Clamping Circuit SINGLE-ENDED MODE OF OPERATION The AD9221/AD9223/AD9220 can be configured for single- ended operation using coupling. In ...

Page 16

AD9221/AD9223/AD9220 AC COUPLING AND INTERFACE ISSUES For applications where ac coupling is appropriate, the op amp’s output can be easily level shifted to the common-mode voltage, VCM, of the AD9221/AD9223/AD9220 via a coupling capacitor. This has the advantage of allowing ...

Page 17

AD828: Dual Version of AD818 Best Applications: Differential and/or Low Imped- ance Input Drivers, Low Noise, Gains ≥ +2 Limits: THD above 100 kHz AD812: Dual, 145 MHz Unity GBW, Single-Supply Cur- rent Feedback ± ...

Page 18

AD9221/AD9223/AD9220 –55 –65 AD9221 AD9223 –75 –85 – FREQUENCY – MHz Figure 18. AD9221/AD9223/AD9220 SFDR vs. Input Frequency ( p-p Input Span –0.5 dB) IN Figure 19 shows the schematic ...

Page 19

Shorting the VREF pin directly to the SENSE pin places the internal reference amplifier in unity-gain mode and the resultant VREF output Therefore, the valid input range However, shorting the SENSE ...

Page 20

AD9221/AD9223/AD9220 The AD9221/AD9223/AD9220 contains an internal reference buffer, A2 (see Figure 9), that simplifies the drive requirements of an external reference. The external reference must be able to drive a ≈5 kΩ (± 20%) load. Note that the bandwidth of ...

Page 21

Table truth table for the over/underrange circuit in Figure 28, which uses NAND gates. Systems requiring programmable gain conditioning of the AD9221/AD9223/ AD9220 input signal can immediately detect an out-of-range condition, thus eliminating gain ...

Page 22

AD9221/AD9223/AD9220 300 280 INPUT = 5V p-p 260 INPUT = 2V p-p 240 220 200 CLOCK FREQUENCY – MHz Figure 29c. AD9220 Power Consumption vs. Clock Frequency GROUNDING AND DECOUPLING Analog and Digital Grounding Proper ...

Page 23

APPLICATIONS Direct IF Down Conversion Using the AD9220 As previously noted, the AD9220’s performance in the differen- tial mode of operation extends well beyond its baseband region and into several Nyquist zone regions. Thus, the AD9220 may be well suited ...

Page 24

AD9221/AD9223/AD9220 The offset calibration circuitry consists of a DAC, U5 and the buffer amplifier, U4. The DAC is configured for a bipolar adjustment span of ± 64 LSB with a 1/2 LSB resolution span with respect to the AD9221/AD9223/AD9220. Note ...

Page 25

TPA D2 1N5711 VINA C19 0 C13 1N5711 15pF NOT C26 INSTALLED 0.1 F C24 C23 10 F 0.1 F TP1 16V A C28 C25 0.1 F 0.1 F +5A A TPB D4 ...

Page 26

AD9221/AD9223/AD9220 Figure 37. Evaluation Board Component Side Layout (Not to Scale) Figure 38. Evaluation Board Solder Side Layout (Not to Scale) –26– REV. E ...

Page 27

Figure 39. Evaluation Board Ground Plane Layout (Not to Scale) REV. E Figure 40. Evaluation Board Power Plane Layout –27– AD9221/AD9223/AD9220 ...

Page 28

AD9221/AD9223/AD9220 Figure 41. Evaluation Board Component Side Silkscreen (Not to Scale) Figure 42. Evaluation Board Component Side Silkscreen (Not to Scale) –28– REV. E ...

Page 29

COPLANARITY 0.10 2.00 MAX 0.05 MIN REV. E OUTLINE DIMENSIONS 28-Lead Standard SmWall Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969 7.60 (0.2992) 7.40 (0.2913) 1 ...

Page 30

AD9221/AD9223/AD9220 Revision History Location 2/03—Data Sheet changed from REV REV. E. Updated graphic captions . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 31

–31– ...

Page 32

–32– ...

Related keywords