AD9229ABCPZRL7-65 Analog Devices Inc, AD9229ABCPZRL7-65 Datasheet - Page 16
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AD9229ABCPZRL7-65
Manufacturer Part Number
AD9229ABCPZRL7-65
Description
Quad 12-Bit 50/65 MSPS, 3V ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9229ABCPZRL7-50.pdf
(40 pages)
Specifications of AD9229ABCPZRL7-65
Number Of Bits
12
Sampling Rate (per Second)
65M
Data Interface
Serial
Number Of Converters
4
Power Dissipation (max)
1.47W
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9229
TERMINOLOGY
Analog Bandwidth
Analog bandwidth is the analog input frequency at which the
spectral power of the fundamental frequency (as determined by
the FFT analysis) is reduced by 3 dB from full scale.
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the 50% point rising
edge of the clock input to the time at which the input signal is
held for conversion.
Aperture Uncertainty (Jitter)
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as frequency-dependent noise
on the ADC input.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Common Mode Rejection Ratio (CMRR)
CMRR is defined as the amount of rejection on the differential
analog inputs when a common signal is applied. Typically
expressed as 20 log (differential gain/common-mode gain).
Crosstalk
Crosstalk is defined as the measure of any feedthrough coupling
onto the quiet channel when all other channels are driven by a
full-scale signal.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a pin and
subtracting the voltage from a second pin that is 180° out of
phase.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to an n-bit resolution indicates that all 2
codes, respectively, must be present over all operating ranges.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the
number of bits. Using the following formula, it is possible to
obtain a measure of performance expressed as N, the effective
number of bits:
N = (SINAD – 1.76)/6.02
n
Rev. B | Page 16 of 40
Full Power Bandwidth
Full power bandwidth is the measured –3 dB point at the analog
front-end input relative to the frequency measured.
Gain Error
The largest gain error is specified and is considered the
difference between the measured and ideal full-scale input
voltage range.
Gain Matching
Expressed as a percentage of FSR and computed using the
following equation:
where FSR
FSR
Input-Referred Noise
Input-referred noise is a measure of the wideband noise
generated by the ADC core. Histograms of the output codes are
created while a dc signal is applied to the ADC input. Input-
referred noise is calculated using the standard deviation of the
histograms and presented in terms of LSB rms.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1.5 LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line.
Noise Power Ratio (NPR)
NPR is the full-scale rms noise power injected into the ADC vs.
the rejected band of interest (notch depth measured).
Offset Error
The largest offset error is specified and is considered the
difference between the measured and ideal voltage at the analog
input that produces the midscale code at the outputs.
Offset Matching
Expressed in millivolts and computed using the following
equation:
where OFF
the most negative offset error.
MIN
Offset Matching = OFF
Gain
is the most negative gain error of the ADCs.
MAX
Matching
MAX
is the most positive gain error of the ADCs, and
is the most positive offset error, and OFF
=
⎛
⎜
⎝
FSR
FSR
MAX
max
max
− OFF
−
+
2
FSR
FSR
MIN
min
min
⎞
⎟
⎠
×
100
%
MIN
is