AD9266BCPZ-20 Analog Devices Inc, AD9266BCPZ-20 Datasheet - Page 17

• Manufacturer Part Number: AD9266BCPZ-20
• Description: 16 Bit, 20 MSPS 1.8V Single ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9266BCPZ-20

• Number Of Bits: 16
• Sampling Rate (per Second): 20M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 63mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The AD9266 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 16-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with
a new input sample, whereas the remaining stages operate with
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS output buffers. The output buffers
are powered from a separate (DRVDD) supply, allowing adjust-
ment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9266 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 35). When the input circuit
is switched to sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current injected from the output
stage of the driving source. In addition, low Q inductors or ferrite
beads can be placed on each leg of the input to reduce high differ-
ential capacitance at the analog inputs and, therefore, achieve
the maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end at
VIN+
VIN–
Figure 35. Switched-Capacitor Input Circuit
C
C
PAR
PAR
H
H
S
S
C
C
SAMPLE
SAMPLE
S
S
H
H
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high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. See the AN-742
Application Note, the AN-827 Application Note, and the Analog
Dialogue article
A/D
general, the precise values depend on the application.
Input Common Mode
The analog inputs of the AD9266 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
a dc bias externally. Setting the device so that VCM = AVDD/2
is recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 36.
An on-board, common-mode voltage reference is included in
the design and is available from the VCM pin. The VCM pin
must be decoupled to ground by a 0.1 μF capacitor, as described
in the Applications Information section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9266 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and
excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9266 (see Figure 37), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
VIN
0.1µF
Converters” (Volume 39, April 2005) for more information. In
Figure 37. Differential Input Configuration Using the ADA4938-2
100
76.8Ω
95
90
85
80
75
70
65
60
0.5
Figure 36. SNR/SFDR vs. Input Common-Mode Voltage,
0.6
120Ω
90Ω
“Transformer-Coupled Front-End for Wideband
INPUT COMMON-MODE VOLTAGE (V)
0.7
f
IN
ADA4938-2
= 32.5 MHz, f
200Ω
200Ω
ADA4938-2
0.8
SNR (dBFS)
SFDR (dBc)
33Ω
33Ω
0.9
S
10pF
= 80 MSPS
differential drivers provide
1.0
1.1
VIN–
VIN+
1.2
ADC
AD9266
AVDD
VCM
1.3