AD9266BCPZ-65 Analog Devices Inc, AD9266BCPZ-65 Datasheet - Page 23
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AD9266BCPZ-65
Manufacturer Part Number
AD9266BCPZ-65
Description
16 Bit, 65 MSPS 1.8V Single ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9266BCPZRL7-20.pdf
(32 pages)
Specifications of AD9266BCPZ-65
Number Of Bits
16
Sampling Rate (per Second)
65M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
113mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TIMING
The AD9266 provides latched data with a pipeline delay of
eight clock cycles. Data outputs are available one propagation
delay (t
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9266. These
transients can degrade converter dynamic performance.
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
PD
) after the rising edge of the clock signal.
Condition (V)
< −VREF − 0.5 LSB
= −VREF
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
Rev. 0 | Page 23 of 32
The lowest typical conversion rate of the AD9266 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD9266 provides a data clock output (DCO) signal that is
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 for
a graphical timing description.
Twos Complement Mode
1000 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1111
AD9266
1
0
1
OR
0
0