AD9267BCPZRL7 Analog Devices Inc, AD9267BCPZRL7 Datasheet
AD9267BCPZRL7
Specifications of AD9267BCPZRL7
Related parts for AD9267BCPZRL7
AD9267BCPZRL7 Summary of contents
Page 1
FEATURES SNR (85 dBFS MHz input SFDR: −88 dBc to 10 MHz input Noise figure Input impedance: 1 kΩ Power: 416 mW 10 MHz real or 20 MHz complex bandwidth 1.8 V analog supply ...
Page 2
AD9267 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ...
Page 3
SPECIFICATIONS DC SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN Table 1. Parameter RESOLUTION ANALOG INPUT BANDWIDTH ACCURACY No Missing Codes Offset Error Gain Error 2 Integral Nonlinearity (INL) ...
Page 4
AD9267 AC SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN Table 2. 2 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz 4.2 MHz ...
Page 5
DIGITAL SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic ...
Page 6
AD9267 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table 4. 1 Parameter CLOCK INPUT PARAMETERS Input CLK Rate CLK± Period CLK± Duty Cycle CLOCK INPUT PARAMETERS Conversion Rate CLK± Period CLK± Duty Cycle DATA ...
Page 7
ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Electrical AVDD to AGND DVDD to DGND DRVDD to DGND AGND to DGND AVDD to DRVDD CVDD to CGND CGND to DGND D0±A to D3±A to DGND D0±B to D3±B to DGND DCO± to ...
Page 8
AD9267 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CVDD PDWNA PDWNB PLL_LOCKED DVDD DGND DRVDD NOTES 1. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO ...
Page 9
TYPICAL PERFORMANCE CHARACTERISTICS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, T otherwise noted. The output spectrums shown in Figure 4 through Figure 9 were obtained after ...
Page 10
AD9267 –50 –60 –70 –80 –90 –100 –110 –120 –130 0 50 100 150 200 FREQUENCY (MHz) Figure 10. Noise Transfer Function (NTF) 120 SFDR 100 (dBFS) 80 SNR (dBFS) SFDR 60 (dBc –100 –90 –80 –70 ...
Page 11
SFDR (dBc) –70 –80 –90 SFDR (dBFS) –100 –110 –120 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) Figure 16. Two-Tone SFDR vs. Input Amplitude with f = 2.1 MHz 2.4 MHz IN1 IN2 –40 –50 ...
Page 12
AD9267 EQUIVALENT CIRCUITS 500Ω 2V p-p DIFFERENTIAL 1.8V CM 500Ω Figure 20. Equivalent Analog Input Circuit CVDD CLK+ 10kΩ 10kΩ 90kΩ 30kΩ CVDD Figure 21. Equivalent Clock Input Circuit DRVDD 1kΩ SDIO Figure 22. Equivalent SDIO Input Circuit CLK– Rev. ...
Page 13
THEORY OF OPERATION The AD9267 uses a continuous time Σ-Δ modulator to convert the analog input to a digital word. The modulator consists of a continuous time loop filter preceding a quantizer (see Figure 27), which samples ...
Page 14
AD9267 Differential Input Configurations Optimum performance can be achieved by driving the AD9267 in a differential input configuration. The ADA4937-2 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4937-2 is ...
Page 15
The second mode bypasses the clock multiplier circuitry and allows the clock to be directly sourced. This mode enables the user to source a very high quality clock directly to the Σ-Δ modulator. Sourcing the clock directly may be necessary ...
Page 16
AD9267 The reference clock, CLK±, is limited to 30 MHz to 160 MHz when configured to use the on-chip clock multiplier. Given the input range of the reference clock and the available multiplica- tion factors, the f is approximately 1280 ...
Page 17
Table 10. PLLMULTx Pins and PLL Multiplication Factor PLLMULT[4:0] Pins PLL Multiplication Factors ( ...
Page 18
AD9267 In normal operation mode, the analog input can toggle the OR±x pin for a number of clock cycles as it approaches full scale. The OR±x pin is a pulse-width modulated (PWM) signal; therefore, as the analog input increases in ...
Page 19
SERIAL PORT INTERFACE (SPI) The AD9267 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending ...
Page 20
AD9267 HARDWARE INTERFACE The pins described in Table 13 comprise the physical interface between the programming device of the user and the serial port of the AD9267. The SCLK and CSB pins function as inputs when using the SPI interface. ...
Page 21
APPLICATIONS INFORMATION FILTERING REQUIREMENT The need for anti-alias protection often requires one or two octaves for a transition band, which reduces the usable bandwidth of a Nyquist converter to between 25% and 50% of the available bandwidth Σ-Δ ...
Page 22
AD9267 Referring to Figure 46, the 3 dB cutoff frequency of the low- pass Chebyshev II filter response resides at 15.75 MHz, and at 10 MHz, there is 0. attenuation due to the sharp roll-off of the filter. ...
Page 23
MEMORY MAP Table 16. Memory Map Register Address (Hex) Bit 7 SPI Port Config 00 0 Chip ID 01 Chip Grade 02 Channel Index 05 Power Modes 08 PLLENABLE 09 PLL 0A PLLLOCKED Output Modes 14 DRVSTD Output Adjust 15 ...
Page 24
AD9267 OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9267BCPZ −40°C to +85°C 1 AD9267EBZ RoHs Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and ...