AD9467BCPZ-250 Analog Devices Inc, AD9467BCPZ-250 Datasheet
AD9467BCPZ-250
Specifications of AD9467BCPZ-250
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AD9467BCPZ-250 Summary of contents
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FEATURES 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 60 fs rms jitter ...
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AD9467 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Absolute ...
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... Full 485 536 580 Full Full Full Full 1.14 1.26 1.37 Full 4.4 90 Rev Page AD9467 AD9467BCPZ-250 Min Typ Max Unit 16 Bits Guaranteed −150 0 +150 LSB −3.5 −0.1 +2.5 %FSR −0.6 ±0.5 +1.3 LSB −11.8 ±3.5 +9.5 LSB ±0.023 %FSR/°C ± ...
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... Full 25°C 93/88 25°C 92/86 Full 100/96 Full 100/98 Full 98/96 Full 96/93 Full 94/93 Full 90/89 Rev Page AD9467BCPZ-250 Max Min Typ Max 2.5 2/2.5 74.7/76.4 74.5/76.1 74.4/76.0 74.7 74.3/75.8 72.3 74.0/75.5 73.3/74.6 74.6/76.3 74.4/76.0 74.4/76.0 74.4 74.2/75.8 71 ...
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... Full 83 25°C 97/96 25°C 98/98 Full 25°C 96/97 25°C 95/95 25°C 95 25°C 93 Rev Page AD9467 AD9467BCPZ-250 Min Typ Max Unit 98/97 dBFS 97/93 dBFS dBFS 97/95 dBFS 90 97/93 dBFS 87 dBFS 97/95 dBFS 97/95 dBFS 97 dBFS ...
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... Full 1.2 3.6 Full 0.3 25°C 30 25°C 0.5 Full 1.7/3.1 Full 0.3 LVDS Full 247 545 Full 1.125 1.375 Offset binary Rev Page AD9467BCPZ-250 Min Typ Max Unit CMOS/LVDS/LVPECL 250 mV p-p 0 kΩ 2.5 pF 1.2 3 kΩ 0 ...
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... 1/fs t CPD t SKEW t PD D15 D14 D15 D14 D15 D14 Figure 2. 16-Bit Output Data Timing Rev Page AD9467BCPZ-250 Min Typ Max Unit 50 250 MSPS 200 ps 200 −200 +200 ps 100 ms 16 Clock cycles 1 rms 1 Clock cycles D15 ...
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AD9467 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To Electrical AVDD1, AVDD3 AGND AVDD2, SPIVDD AGND DRVDD DRGND AGND DRGND AVDD2, SPIVDD AVDD1, AVDD3 AVDD1, AVDD3 DRVDD AVDD2, SPIVDD DRVDD Digital Outputs (Dx+, DRGND Dx−, OR+, OR−, DCO+, DCO−) ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 DRGND DRVDD NOTES 1. DNC = DO NOT CONNECT. 2. EXPOSED THERMAL PAD MUST BE CONNECTED TO AGND. Table 7. Pin Function Descriptions Pin ...
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AD9467 Pin No Mnemonic Description D15+/D14+ D15 (MSB) and D14 Digital Output True. DCO− Data Clock Digital Output Complement. DCO+ Data Clock Digital Output True. OR− Out-of-Range Digital Output Complement. ...
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EQUIVALENT CIRCUITS AVDD2 VIN+ BUF 265Ω BUF AVDD2 265Ω VIN– BUF Figure 4. Equivalent Analog Input Circuit AVDD1 10kΩ 0.8V 10kΩ 10kΩ CLK+ Figure 5. Equivalent Clock Input Circuit DRVDD V Dx– V DRGND Figure 6. Equivalent Digital Output Circuit ...
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AD9467 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 1.8 V, AVDD2 = 3.3 V, AVDD3 = 1.8 V, DRVDD = 1.8 V, specified maximum sampling rate, 2.5 V p-p differential input, 1.25 V internal reference, AIN = −1.0 dBFS, DCS on, default ...
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FREQUENCY (MHz) Figure 16. Single-Tone FFT with f = 4.3 MHz, 2.5 V p-p FS, AD9467-250 IN 0 AIN = –1.0dBFS SNR = 75.9dBFS –20 ENOB = 12.3 ...
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AD9467 78 77 SNR 76 SFDR 100 120 140 160 180 SAMPLE RATE (MSPS) Figure 22. SNR/SFDR vs 97.3 MHz, 2.5 V p-p FS, AD9467-200 SAMPLE SNR ...
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AIN1 AND AIN2 = –7dBFS SFDR = 94.6dBFS –20 IMD2 = 94.6dBFS IMD3 = 95.9dBFS –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 28. Two-Tone FFT with ...
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AD9467 100 SFDR SINAD 75 70 TEMPERATURE (°C) Figure 34. SINAD/SFDR vs. Temperature, f 2.5 V p-p FS, AD9467-200 100 SFDR SINAD 75 70 TEMPERATURE (°C) Figure 35. SINAD/SFDR vs. Temperature, f ...
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SFDR 90 80 SNR DEFAULT CMV 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 40. SNR/SFDR vs. Analog Input Common-Mode Voltage, AIN = 100 MHz, 2.5 V ...
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AD9467 –55 –60 –65 AVDD2 –70 AVDD1 –75 –80 DRVDD –85 –90 ANALOG INPUT FREQUENCY (MHz) Figure 46. Power Supply Rejection (PSR), AD9467-250 100 100 150 BUFFER CURRENT PERCENTAGE (%) Figure 47. ...
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... MSPS and 200 MSPS parts. For example, when using IFs from 150 MHz to 250 MHz, 160% is actually the average of the entire buffer current. Therefore, both Register 36 and Register 107 need to be set to 160%. AD9467BCPZ-250 buffer current settings: • 150 MHz at 80% (default setting) • ...
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... AD9467 AD9467BCPZ-200 buffer current settings: • 150 MHz at 80% (default setting) • 150 MHz to 250 MHz at 100% • 250 MHz and higher at 160% 100 100 150 ANALOG INPUT FREQUENCY (MHz) Figure 50. Buffer Current Sweeps, 2.5 V p-p, AD9467-200 Note that for sample rates less than 150 MSPS and analog inputs less than 100 MHz recommended to set the buffer current to 0% ...
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RATIO ADL5562 50Ω AC 0.1µF 40Ω Figure 54. Wideband Differential Amplifier Input Configuration Using the 0 AIN = –1dBFS SNR = 73.8dBFS SFDR = 91.1dBFS – 100MHz f = 250MSPS –30 S –45 –60 ...
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AD9467 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9467 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins ...
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Power Dissipation and Power-Down Mode As shown in Figure 62, the power dissipated by the AD9467 is proportional to its sample rate. The output power dissipation does not vary much because it is determined primarily by the DRVDD supply and ...
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AD9467 CLOCK 1 DCO 2 3 DATA CH1 500mV Ω 5.0ns/DIV CH2 500mV Ω 20.0GS/s IT 25.0pt/pt CH3 500mV Ω Figure 64. Output Timing Example in LVDS Mode (Default), AD9467-250 An example of the LVDS output using the ANSI-644 standard ...
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There are eight digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 10 for the output bit sequencing options available. Some test ...
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AD9467 SERIAL PORT INTERFACE (SPI) The AD9467 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization, depending ...
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CSB SCLK DON’T CARE R A12 SDIO DON’T CARE Table 12. Serial Timing Definitions Parameter Timing (Minimum, ns CLK ...
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AD9467 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (see Table 13) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address ...
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Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 ADC Functions 08 modes test_io adc_input XVREF off (default) 10 offset 14 output_mode output_adjust X X ...
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AD9467 Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 18 vref analog_input Buffer Current Select 1 107 Buffer Current Select undefined feature, don’t write. Bit 5 Bit 4 Bit ...
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Power and Ground Recommendations When connecting power to the AD9467 recommended that three separate supplies be used: one for analog AVDD1 and AVDD3 (1.8 V), one for analog AVDD2 (3.3 V), and one for digital output drivers DRVDD ...
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... Figure 70. 72-Lead Lead Frame Chip Scale Package, Exposed Pad [LFCSP_VQ] ORDERING GUIDE 1 Model Temperature Range AD9467BCPZ-200 –40°C to +85°C AD9467BCPZRL7-200 –40°C to +85°C AD9467BCPZ-250 –40°C to +85°C AD9467BCPZRL7-250 –40°C to +85°C AD9467-200EBZ AD9467-250EBZ RoHS Compliant Part. ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...