AD9510/PCBZ Analog Devices Inc, AD9510/PCBZ Datasheet - Page 12

• Manufacturer Part Number: AD9510/PCBZ
• Description: 800MHz PLL Clock Dist Eval Bd.
• Manufacturer: Analog Devices Inc

Specifications of AD9510/PCBZ

• Main Purpose: Timing, Clock Distribution
• Utilized Ic / Part: AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9510
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 6.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
LVDS OUTPUT ADDITIVE TIME JITTER
CLK1 = 622.08 MHz
CLK1 = 622.08 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT3) = 622.08 MHz
Divide Ratio = 1
Any LVPECL (OUT0 to OUT3) = 155.52 MHz
Divide Ratio = 4
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 100 MHz
All LVDS (OUT4 to OUT7) = 100 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
All LVDS (OUT4 to OUT7) = 50 MHz
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs Off)
Any LVPECL (OUT0 to OUT3) = 100 MHz
Divide Ratio = 4
All Other LVPECL = 50 MHz
All CMOS (OUT4 to OUT7) = 50 MHz (B Outputs On)
LVDS (OUT4, OUT7) = 100 MHz
Divide Ratio = 4
LVDS (OUT5, OUT6) = 100 MHz
Divide Ratio = 4
Rev. A | Page 12 of 60
Min
Typ
40
55
215
215
222
225
225
264
319
Max
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Distribution Section only;
does not include PLL or external VCO/VCXO
BW = 12 kHz − 20 MHz (OC-12)
BW = 12 kHz − 20 MHz (OC-3)
Calculated from SNR of ADC method;
F
Calculated from SNR of ADC method;
F
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
F
Interferer(s)
Calculated from SNR of ADC method;
F
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
F
Interferer(s)
Distribution Section only;
does not include PLL or external VCO/VCXO
Calculated from SNR of ADC method;
F
Calculated from SNR of ADC method;
F
Test Conditions/Comments
Interferer(s)
Interferer(s)
C
C
C
C
C
C
C
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
= 100 MHz with A
IN
IN
IN
IN
IN
IN
IN
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz
= 170 MHz