AD9510/PCBZ Analog Devices Inc, AD9510/PCBZ Datasheet - Page 14

• Manufacturer Part Number: AD9510/PCBZ
• Description: 800MHz PLL Clock Dist Eval Bd.
• Manufacturer: Analog Devices Inc

Specifications of AD9510/PCBZ

• Main Purpose: Timing, Clock Distribution
• Utilized Ic / Part: AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9510
Parameter
DELAY BLOCK ADDITIVE TIME JITTER
1
PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS
Table 7.
Parameter
PHASE NOISE AND SPURIOUS
VCXO = 245.76 MHz,
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
CLK1 = 400 MHz
100 MHz Output
F
245.76 MHz Output
61.44 MHz Output
PFD
Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
All Other CMOS = 50 MHz (B Output On)
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100
Spurious
Spurious
Phase Noise @100 kHz Offset
Phase Noise @100 kHz Offset
= 1.2288 MHz; R = 25, N = 200
1
Min
Typ
<−145
<−97
<−155
<−97
Max
Rev. A | Page 14 of 60
Min
Unit
dBc/Hz
dBc
dBc/Hz
dBc
Typ
555
0.61
0.73
0.71
1.2
0.86
1.8
1.2
2.1
1.3
2.7
2.0
2.8
Max
Test Conditions/Comments
Depends on VCO/VCXO selection. Measured at LVPECL
clock outputs; ABP = 6 ns; I
VCXO is Toyocom TCO-2112 245.76.
Divide by 1.
Dominated by VCXO phase noise.
First and second harmonics of F
floor.
Divide by 4.
Dominated by VCXO phase noise.
First and second harmonics of F
floor.
Unit
fs rms
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Calculated from SNR of ADC method;
F
Interferer(s)
Incremental additive jitter
Test Conditions/Comments
Interferer(s)
C
= 100 MHz with A
CP
= 5 mA; Ref = 30.72 MHz.
PFD.
PFD.
. Below measurement
. Below measurement
IN
= 170 MHz
1