AD9516-4BCPZ Analog Devices Inc, AD9516-4BCPZ Datasheet - Page 43

• Manufacturer Part Number: AD9516-4BCPZ
• Description: Clock IC With 1.8GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-4BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9516-4/PCBZ - BOARD EVAL FOR AD9516-4 1.8GHZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIVIDER 0
DIVIDER 1
DIVIDER 2
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 38).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset or delay the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register, plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M) that
are programmed for the divider.
The SYNC function must be used to make phase offsets effective
(see the Synchronizing the Outputs—SYNC Function section).
Table 38. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 2
Divider
0
1
2
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to D
T
(in seconds).
Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles, and M = low cycles.
Case 1
For Φ ≤ 15:
Δt = Φ × T
Δc = Δt/T
Case 2
For Φ ≥ 16:
Δt = (Φ − 16 + M + 1) × T
Δc = Δt/T
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 55 shows the results of setting such a coarse
offset between outputs.
DIVIDER INPUT
X
= period of the clock signal at the input of the divider, D
CHANNEL
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
X
X
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
X
= Φ
Figure 55. Effect of Coarse Phase Offset (or Delay)
0
1
Tx
2
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
3
X
1 × Tx
2 × Tx
4
5
6
7
8
Low
Cycles (M)
0x190[7:4]
0x193[7:4]
0x196[7:4]
9 10 11 12 13 14 15
X
).
High
Cycles (N)
0x190[3:0]
0x193[3:0]
0x196[3:0]
X
Rev. A | Page 43 of 80
Channel Dividers—LVDS/CMOS Outputs
Channel Divider 3 and Channel Divider 4 each drive a pair of
LVDS outputs, giving a total of four LVDS outputs (OUT6 to
OUT9). Alternatively, each of these LVDS differential outputs
can be configured individually as a pair (A and B) of CMOS
single-ended outputs, providing for up to eight CMOS outputs.
By default, the B output of each pair is off but can be turned on
as desired.
Channel Divider 3 and Channel Divider 4 each consist of two
cascaded, 2 to 32, frequency dividers. The channel frequency
division is D
bypassing one or both of these dividers. Both of the dividers
also have DCC enabled by default, but this function can be
disabled, if desired, by setting the DCCOFF bit of the channel.
A coarse phase offset or delay is also programmable (see the
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
section). The channel dividers operate up to 1600 MHz. The
features and settings of the dividers are selected by programming
the appropriate setup and control registers (see Table 52 and
Table 53 through Table 62).
Table 39. Setting Division (D
Divider
3
4
1
Channel Frequency Division (Divider 3 and Divider 4)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2)
When both X.1 and X.2 are bypassed, D
When only X.2 is bypassed, D
When both X.1 and X.2 are not bypassed, D
(N
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (D
If only one divider is needed when using Divider 3 and Divider 4,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
Note that the value stored in the register = # of cycles minus 1.
X.2
Number of Low Cycles = M
Number of High Cycles = N
+ M
3.1
3.2
4.1
4.2
X.2
M
0x199[7:4]
0x19B[7:4]
0x19E[7:4]
0x1A0[7:4]
+ 2).
X.1
× D
X.2
or up to 1024. Divide-by-1 is achieved by
N
0x199[3:0]
0x19B[3:0]
0x19E[3:0]
0x1A0[3:0]
X
X
= (N
) for Divider 3, Divider 4
X.Y
X.Y
+ 1
+ 1
X.1
X.1
+ M
Bypass
0x19C[4]
0x19C[5]
0x1A1[4]
0x1A1[5]
X
× D
= 1 × 1 = 1.
X
X.1
= (N
X.2
+ 2) × 1.
) can be realized.
X.1
AD9516-4
+ M
DCCOFF
0x19D[0]
0x19D[0]
0x1A2[0]
0x1A2[0]
X.1
+ 2) ×
1