AD9516-4BCPZ Analog Devices Inc, AD9516-4BCPZ Datasheet - Page 47

• Manufacturer Part Number: AD9516-4BCPZ
• Description: Clock IC With 1.8GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-4BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9516-4/PCBZ - BOARD EVAL FOR AD9516-4 1.8GHZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A sync operation brings all outputs that have not been excluded
(by the nosync bit) to a preset condition before allowing the
outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static
state of each output when the SYNC operation is happening and
the state and relative phase of the outputs when they begin
clocking again upon completion of the SYNC operation.
Between outputs and after synchronization, this allows for the
setting of phase offsets.
The AD9516 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
SYNC PIN
IINPUT TO CHANNEL DIVIDER
INPUT TO CHANNEL DIVIDER
SYNC PIN
INPUT TO VCO DIVIDER
CHANNEL DIVIDER
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
INPUT TO CLK
OUTPUT OF
OUTPUT OF
Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
1
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
2
2
3
3
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER OUTPUT STATIC
Rev. A | Page 47 of 80
4
4
5
5
6
6
Each channel (a divider and its outputs) can be excluded from
any sync operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a sync operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
Clock Outputs
The AD9516 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0 to OUT5 are LVPECL
differential outputs; and OUT6 to OUT9 are LVDS/CMOS
outputs. These outputs can be configured as either LVDS
differential or as pairs of single-ended CMOS outputs.
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
1
1
OUTPUT CLOCKING
OUTPUT CLOCKING
CHANNEL DIVIDER
CHANNEL DIVIDER
AD9516-4