AD9517-0ABCPZ Analog Devices Inc, AD9517-0ABCPZ Datasheet - Page 60
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AD9517-0ABCPZ
Manufacturer Part Number
AD9517-0ABCPZ
Description
12-Output Clock Generator With 2.8GHz VC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-0ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-0ABCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
2.95GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.95GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
40
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9517-0ABCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9517-0
Reg.
Addr.
(Hex)
0x016
0x017
Bits
[2:0]
[7:2]
Name
Prescaler P
STATUS pin
control
Description
Prescaler: DM = dual modulus and FD = fixed divide.
2
0
0
0
0
1
1
1
1
Select the signal that is connected to the STATUS pin.
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
6
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
5
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4
0
0
0
0
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mode
FD
FD
DM
DM
DM
DM
DM
FD
3
0
0
1
1
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Prescaler
Divide-by-1.
Divide-by-2.
Divide-by-2 (2/3 mode).
Divide-by-4 (4/5 mode).
Divide-by-8 (8/9 mode).
Divide-by-16 (16/17 mode).
Divide-by-32 (32/33 mode) (default).
Divide-by-3.
2
0
1
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. B | Page 60 of 80
Level or
Dynamic
Signal
LVL
DYN
DYN
DYN
DYN
DYN
DYN
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
A divider output.
REF1 clock (differential reference when in differential mode).
Selected reference to PLL (differential reference when in differential mode).
(DLD) AND (status of selected reference) AND (status of VCO).
Signal at STATUS Pin
Ground (dc) (default).
N divider output (after the delay).
R divider output (after the delay).
Prescaler output.
PFD up pulse.
PFD down pulse.
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
Ground (dc).
REF2 clock (N/A in differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference); active
high.
Status of unselected reference (not available in differential mode);
active high.
Status REF1 frequency (active high).
Status REF2 frequency (active high).
(Status REF1 frequency) AND (status REF2 frequency).
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active high.
Holdover active (active high).
LD pin comparator output (active high).
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in differential mode).
Unselected reference to PLL (not available when in differential mode).
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD) (active low).
Holdover active (active low).
LD pin comparator output (active low).