AD9517-0ABCPZ Analog Devices Inc, AD9517-0ABCPZ Datasheet - Page 73
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AD9517-0ABCPZ
Manufacturer Part Number
AD9517-0ABCPZ
Description
12-Output Clock Generator With 2.8GHz VC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-0ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-0ABCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
2.95GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.95GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
40
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9517-0ABCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Reg.
Addr.
(Hex)
0x19F
0x1A0
0x1A1
0x1A2
Bits
[7:4]
[3:0]
[7:4]
[3:0]
5
4
3
2
1
0
0
Name
Phase Offset Divider 3.2
Phase Offset Divider 3.1
Low Cycles Divider 3.2
High Cycles Divider 3.2
Bypass Divider 3.2
Bypass Divider 3.1
Divider 3 nosync
Divider 3 force high
Start High Divider 3.2
Start High Divider 3.1
Divider 3 DCCOFF
Description
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass (and power-down) 3.2 divider logic; route clock to 3.2 output.
0: do not bypass (default).
1: bypass.
Bypass (and power-down) 3.1 divider logic; route clock to 3.1 output.
0: do not bypass (default).
1: bypass.
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
0: force low (default).
1: force high.
Divider 3.2 start high/low.
0: start low (default).
1: start high.
Divider 3.1 start high/low.
0: start low (default).
1: start high.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Rev. B | Page 73 of 80
AD9517-0