AD9520-2/PCBZ Analog Devices Inc, AD9520-2/PCBZ Datasheet - Page 28

• Manufacturer Part Number: AD9520-2/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-2/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-2
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9520 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 49 to Table 60). Each section or function must be
individually programmed by setting the appropriate bits in the
corresponding control register or registers. When the desired
configuration is programmed, the user can store these values in
the on-board EEPROM to allow the part to power up in the desired
configuration without user intervention.
Mode 0: Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed its specified maximum frequency (see
Table 3). The internal PLL uses an external loop filter to set the
loop bandwidth. The external loop filter is also crucial to the
loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, the
register settings shown in Table 22 should be used.
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Table 22. Settings When Using Internal VCO
Register
0x010[1:0] = 00b
0x010 to 0x01E
0x1E1[1] = 1b
0x01C[2:0]
0x1E0[2:0]
0x1E1[0] = 0b
0x018[0] = 0b
0x232[0] = 1b
0x018[0] = 1b
0x232[0] = 1b
Description
PLL normal operation (PLL on)
PLL settings; select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
according to the intended loop configuration
VCO selected as the source
Enable reference inputs
Set VCO divider
Use the VCO divider as the source for the
distribution section
Reset VCO calibration and issue IO_UPDATE
(not necessary for the first time after power-
up but must be done subsequently)
Initiate VCO calibration, issue IO_UPDATE
CP