AD9520-2/PCBZ Analog Devices Inc, AD9520-2/PCBZ Datasheet - Page 41

• Manufacturer Part Number: AD9520-2/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-2/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

After leaving holdover, the loop then reacquires lock, and the
LD pin must go high (if 0x01D[3] = 1) before it can reenter
holdover.
The holdover function always responds to the state of the
currently selected reference (0x01C). If the loop loses lock
during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the automatic/internal holdover
function:
•
•
•
•
•
•
OPTIONAL
0x018[6:5]—lock detect counter. This changes how many
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate
lock. This impacts the time required before the LD pin can
begin to charge as well as the delay from the end of a
holdover event until the holdover function can be reengaged.
0x018[3]—disable digital lock detect. This bit must be set
to a 0 to enable the DLD circuit. Internal/automatic
holdover does not operate correctly without the DLD
function enabled.
0x01A[5:0]—lock detect pin control. Set this to 000100b to
put it in the current source lock detect mode if using the
LD pin comparator. Load the LD pin with a capacitor of an
appropriate value.
0x01D[3]—LD pin comparator enable. 1 = enable; 0 =
disable. When disabled, the holdover function always
senses the LD pin as high.
0x01D[1]—external holdover control.
0x01D[0]—holdover enable. If holdover is disabled, both
external- and automatic/ internal holdover are disabled.
BYPASS
REFIN
REFIN
CLK
CLK
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
BUF
SWITCHOVER
STATUS
REFERENCE
REF_SEL
STATUS
VS
PRESCALER
ZERO DELAY BLOCK
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
P, P + 1
GND
0
VCO STATUS
Figure 47. Reference and VCO Status Monitors
N DIVIDER
COUNTERS
DISTRIBUTION
REFERENCE
A/B
Rev. 0 | Page 41 of 84
RSET
FROM CHANNEL
PROGRAMMABLE
DIVIDER 0
REFMON
In the following example, automatic holdover is configured with
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•
•
The following registers are set (in addition to the normal PLL
registers):
•
•
•
•
•
•
•
•
•
•
Frequency Status Monitors
The AD9520 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 47.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 17). The reference frequency
monitor thresholds are selected in 0x01F.
N DELAY
Automatic reference switchover, prefer REF1.
Digital lock detect: five PFD cycles, high range window.
Automatic holdover using the LD pin comparator.
0x018[6:5] = 00b; lock detect counter = five cycles.
0x018[4] = 0b; digital lock detect window = high range.
0x018[3] = 1b; disable DLD normal operation.
0x01A[5:0] = 000100b; program LD pin control to current
source lock detect mode.
0x01C[4] = 1b; enable automatic switchover.
0x01C[3] = 0b; prefer REF1.
0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
0x01D[3] = 1b; enable LD pin comparator.
0x01D[1] = 0b; disable external holdover mode and use
automatic/internal holdover mode.
0x01D[0] = 1b; enable holdover.
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
CPRSET VCP
CHARGE
PUMP
HOLD
AD9520-2
LD
CP
STATUS
VS_DRV