AD9520-5BCPZ Analog Devices Inc, AD9520-5BCPZ Datasheet - Page 39

• Manufacturer Part Number: AD9520-5BCPZ
• Description: 12/24-Output Clock Generator
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-5BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.6GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK DISTRIBUTION
A clock channel consists of three LVPECL clock outputs or six
CMOS clock outputs that share a common divider. A clock
output consists of the drivers that connect to the output pins.
The clock outputs have either LVPECL or CMOS at the pins.
The AD9520 has four clock channels. Each channel has its own
programmable divider that divides the clock frequency applied
to its input. The channel dividers can divide by any integer from
1 to 32.
The AD9520 features a VCO divider that divides the CLK input by
1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.
The VCO divider has two purposes. The first is to limit the
maximum input frequency of the channel dividers to 1.6 GHz.
The other is to allow the AD9520 to generate even lower
frequencies than would be possible with only a simple post divider.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 15 input clock cycles. For example, if
the frequency at the input of the channel divider is 1 GHz, the
channel divider output can be delayed by up to 15 ns. The
divider outputs can also be set to start high or to start low.
CLK
CLK
MODE 1 (CLOCK DISTRIBUTION MODE)
Figure 37. Simplified Diagram of the Two Clock Distribution Operation Modes
DISTRIBUTION
CLOCK
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
0
PLL
BUTION
CLOCK
DISTRI-
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CLK
CLK
MODE 2 (HF CLOCK DISTRIBUTION MODE)
Operation Modes
There are two clock distribution operating modes, and these are
shown in Figure 37.
It is not necessary to use the VCO divider if the CLK frequency
is less than the maximum channel divider input frequency
(1600 MHz); otherwise, the VCO divider must be used to
reduce the frequency going to the channel dividers.
Table 26 shows how the operation modes are selected. 0x1E1[0]
selects the channel divider source.
Table 26. Operation Modes
Mode
2
1
CLK Direct-to-LVPECL Outputs
It is possible to connect the CLK directly to the LVPECL
outputs. However, the LVPECL outputs may not be able to meet
the V
To connect the LVPECL outputs directly to the CLK input, the
user must select the VCO divider as the source to the distribution
section, even if no channel uses it.
Table 27. Routing VCO Divider Input Directly to the Outputs
Register Setting
0x1E1[0] = 0b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
0x19B[1] = 1b
OD
specification in Table 4 above 1600 MHz.
0x1E1[0]
0
1
DISTRIBUTION
CLOCK
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
CLK is the source; VCO divider selected
Selection
Direct-to-output OUT0, OUT1, OUT2
Direct-to-output OUT3, OUT4, OUT5
Direct-to-output OUT6, OUT7, OUT8
Direct-to-output OUT9, OUT10, OUT11
0
PLL
BUTION
DISTRI-
CLOCK
VCO Divider
Used
Not used
AD9520-5