AD9520-5BCPZ Analog Devices Inc, AD9520-5BCPZ Datasheet - Page 45
![12/24-Output Clock Generator](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9520-5BCPZ
Manufacturer Part Number
AD9520-5BCPZ
Description
12/24-Output Clock Generator
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9520-5BCPZ.pdf
(80 pages)
Specifications of AD9520-5BCPZ
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.6GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9520-5BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
When the AD9520 is in a PD power-down, the chip is in the
following state:
•
•
•
•
•
•
•
•
PLL Power-Down
The PLL section of the AD9520 can be selectively powered
down. There are two PLL power-down modes set by
Register 0x010[1:0]: asynchronous and synchronous.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated. In synchronous power-down
mode, the PLL power-down is gated by the charge pump to
prevent unwanted frequency jumps. The device goes into power-
down on the occurrence of the next charge pump event after the
registers are updated.
The PLL is off (asynchronous power-down).
The CLK input buffer is off, but the CLK input dc bias
circuit is on.
In differential mode, the reference input buffer is off, but
the dc bias circuit is still on.
In singled-ended mode, the reference input buffer is off,
and the dc bias circuit is off.
All dividers are off.
All CMOS outputs are tristated.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
Rev. 0 | Page 45 of 80
Distribution Power-Down
The distribution section can be powered down by writing
0x230[1] = 1b, which turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(0b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to 1b, the LVPECL output
is not protected from reverse bias and can be damaged under
certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
into safe power-down mode by individually writing to the
appropriate registers. The register map details the individual
power-down settings for each output. These settings are found
in Register 0x0F0[0] to Register 0x0FB[0].
Individual Clock Channel Power-Down
Any of the clock distribution channels can be powered down
individually by writing to the appropriate registers. Powering
down a clock channel is similar to powering down an individual
driver, but it saves more power because the dividers are also
powered down. Powering down a clock channel also automatically
powers down the drivers connected to it. The register map
details the individual power-down settings for each output
channel. These settings are found in 0x192[2], 0x195[2],
0x198[2], and 0x19B[2].
AD9520-5