AD9522-3BCPZ Analog Devices Inc, AD9522-3BCPZ Datasheet

12- Channel Clock Generator With Integra

AD9522-3BCPZ

Manufacturer Part Number
AD9522-3BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet

Specifications of AD9522-3BCPZ

Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.25GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Price
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Manufacturer:
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Quantity:
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FEATURES
Low phase noise, phase-locked loop (PLL)
Twelve 800 MHz LVDS outputs divided into 4 groups
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9522-3
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz
to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
1
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-3 is used, it is referring to that specific
member of the AD9522 family.
On-chip VCO tunes from 1.72 GHz to 2.25 GHz
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVPECL, or LVDS references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Auto and manual reference switchover/holdover modes,
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Each group of 3 has a 1-to-32 divider with phase delay
Additive output jitter as low as 245 fs rms
Channel-to-channel skew grouped outputs <60 ps
Each LVDS output can be configured as 2 CMOS outputs
and other 10 Gbps protocols
with selectable revertive/nonrevertive switching
(for f
OUT
≤ 250 MHz)
1
provides a multioutput clock distribution
12 LVDS/24 CMOS Output Clock Generator
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The AD9522 serial interface supports both SPI and I2C® ports.
An in-package EEPROM can be programmed through the
serial interface and store user-defined register settings for
power-up and chip reset.
The AD9522 features 12 LVDS outputs in four groups. Any of
the 800 MHz LVDS outputs can be reconfigured as two
250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide
ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9522 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage up to 5.5 V.
The AD9522 is specified for operation over the standard industrial
range of −40°C to +85°C.
The
LVPECL/CMOS drivers instead of LVDS/CMOS drivers.
OPTIONAL
AD9520-3
REFIN
REFIN
with Integrated 2 GHz VCO
CLK
FUNCTIONAL BLOCK DIAGRAM
is an equivalent part to the AD9522-3 featuring
SPI/I
DIGITAL LOGIC
REF1
REF2
PORT AND
2
C CONTROL
©2008 Analog Devices, Inc. All rights reserved.
AND MUXES
DIVIDER
Figure 1.
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
CP
EEPROM
VCO
LF
LVDS/
CMOS
AD9522-3
AD9522
MONITOR
STATUS
DELAY
ZERO
www.analog.com
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11

Related parts for AD9522-3BCPZ

AD9522-3BCPZ Summary of contents

Page 1

... GHz. An external 3.3 V/5 V VCO/VCXO 2.4 GHz can also be used. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-3 is used referring to that specific member of the AD9522 family. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...

Page 2

... AD9522-3 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 8 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 9 Clock Output Absolute Phase Noise (Internal VCO Used Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ...

Page 3

... Thermal Performance ..................................................................... 60   Register Map .................................................................................... 61   Register Map Descriptions ............................................................. 66   Applications Information ............................................................... 80   Frequency Planning Using the AD9522 .................................. 80   Using the AD9522 Outputs for ADC Clock Applications .... 80   LVDS Clock Distribution ........................................................... 80   CMOS Clock Distribution ......................................................... 81   Outline Dimensions ........................................................................ 82   Ordering Guide ........................................................................... 82   ...

Page 4

... AD9522-3 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5. (min) and maximum (max) values are given over full VS and T POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ VS 3.135 3.3 VCP VS RSET Pin Resistor 4.12 CPRSET Pin Resistor 5.1 BYPASS Pin Capacitor ...

Page 5

... Register 0x019[2:0]; see Table 52 Off 385 ps 504 ps 623 ps 743 ps 866 ps 989 ps 1112 ps Register 0x019[5:3]; see Table 52 Off 365 ps 486 ps 608 ps 730 ps 852 ps 976 ps 1101 ps Rev Page AD9522-3 is possible by changing CP is possible by changing < VCP − 0 the voltage on the CP (charge CP CP < VCP − 0 ...

Page 6

... AD9522-3 Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode ...

Page 7

... V Rev Page AD9522-3 Test Conditions/Comments Termination = 100 Ω across differential pair Differential (OUT, OUT) The AD9522 outputs toggle at higher frequencies, but the output amplitude may not meet the V specification See Figure 21 Output shorted to GND Single-ended; termination = 10 pF See Figure load ...

Page 8

... AD9522-3 TIMING CHARACTERISTICS Table 5. Parameter LVDS OUTPUT RISE/FALL TIMES Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVDS OUTPUT LVDS For All Divide Values Variation with Temperature 1 OUTPUT SKEW, LVDS OUTPUTS LVDS Outputs That Share the Same Divider LVDS Outputs on Different Dividers ...

Page 9

... Input slew rate > 1 V/ns −102 dBc/Hz −114 dBc/Hz −122 dBc/Hz −129 dBc/Hz −135 dBc/Hz −140 dBc/Hz −150 dBc/Hz Input slew rate > 1 V/ns −125 dBc/Hz −136 dBc/Hz −144 dBc/Hz −152 dBc/Hz −157 dBc/Hz −160 dBc/Hz −164 dBc/Hz Rev Page AD9522-3 ...

Page 10

... AD9522-3 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVDS ABSOLUTE PHASE NOISE VCO = 2250 MHz; Output = 750 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 1985 MHz; Output = 662 MHz @ 1 kHz Offset ...

Page 11

... Integration bandwidth = 12 kHz to 20 MHz 263 fs rms Calculated from SNR of ADC method Broadband jitter 242 fs rms Calculated from SNR of ADC method Broadband jitter Distribution section only; does not include PLL and VCO 289 fs rms Calculated from SNR of ADC method Broadband jitter Rev Page AD9522-3 ...

Page 12

... CS has an internal 30 kΩ pull-up resistor 2 μA −110 μA The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor 2 pF SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I 2.0 V 0.8 V 110 μ ...

Page 13

... VS) and VIL MIN (0.7 × VS) 400 kHz μs μs μs μs μs μs 300 ns 300 ns ns This is a minor deviation from the original I²C specification of 100 ns minimum 880 ns This is a minor deviation from the original I²C specification minimum 400 pF AD9522-3 levels MAX ...

Page 14

... Test Conditions/Comments Each of these pins has a 30 kΩ internal pull-up resistor 2 μA −110 μA The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor 100 ns 1.3 ns High speed clock is CLK input signal Unit ...

Page 15

... Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by- Rev Page AD9522-3 = 250 MHz; VCO = 2000 MHz; VCO divider = 2; OUT = 62.5 MHz; VCO = 2000 MHz; VCO divider = 2; OUT = 200 MHz; VCO divider = 2; one LVDS output OUT = 200 MHz; VCO divider bypassed; one LVDS OUT = 62 ...

Page 16

... AD9522-3 ABSOLUTE MAXIMUM RATINGS Table 19. With Parameter or Pin Respect to VS GND VCP, CP GND REFIN, REFIN GND RSET, LF, BYPASS GND CPRSET GND CLK, CLK GND CLK CLK SCLK/SCL, SDIO/SDA, SDO, CS GND OUT0, OUT0, OUT1, OUT1, GND OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, ...

Page 17

... Along with CLK, this pin is the differential input for the clock distribution section. Along with CLK, this pin is the differential input for the clock distribution section single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor from this pin to ground. Rev Page AD9522-3 48 OUT3 (OUT3A) 47 OUT3 (OUT3B) ...

Page 18

... Three-level logic. This pin is internally biased for the open logic level. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9522 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 kΩ ...

Page 19

... Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. The exposed die pad must be connected to GND. Rev Page AD9522-3 ...

Page 20

... AD9522-3 TYPICAL PERFORMANCE CHARACTERISTICS 275 3 CHANNELS—6 LVDS 250 225 3 CHANNELS—3 LVDS 200 175 2 CHANNELS—2 LVDS 150 125 1 CHANNEL—1 LVDS 100 75 0 200 400 600 FREQUENCY (MHz) Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and VCO Divider Bypassed, LVDS Outputs Terminated 100 Ω Across Differential Pair 240 2 CHANNELS— ...

Page 21

... Figure 16. CMOS Output V 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 135 140 145 0 Rev Page AD9522-3 122.58 122.78 122.98 123.18 FREQUENCY (MHz) LBW = 127 kHz 3.0 mA 1720 MHz CP VCO VS_DRV = 3.3V VS_DRV = 3.135V VS_DRV = 2.5V VS_DRV = 2.35V 1k RESISTIVE LOAD (Ω) (Static) vs ...

Page 22

... AD9522-3 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.5 1.0 1.5 TIME (ns) Figure 18. LVDS Differential Voltage Swing @ 800 MHz Output Terminated 100 Ω Across Differential Pair 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0 TIME (ns) Figure 19. CMOS Output with 10 pF Load @ 25 MHz 2pF LOAD 3 ...

Page 23

... Figure 27. Additive (Residual) Phase Noise, CLK-to-LVDS @ 200 MHz, Divide-by-5 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 28. Additive (Residual) Phase Noise, CLK-to-LVDS @ 800 MHz, Divide-by-1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS @ 50 MHz, Divide-by-20 AD9522-3 10M 100M 10M 100M 10M 100M ...

Page 24

... AD9522-3 –100 –110 –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @ 250 MHz, Divide-by-4 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @ 1720 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz – ...

Page 25

... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9522-3 ...

Page 26

... REGULATOR (LDO) LF CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522 VS GND RSET REFMON DISTRIBUTION REFERENCE STATUS PROGRAMMABLE A/B N DELAY PRESCALER COUNTERS N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE ...

Page 27

... THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9522 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 48 to Table 59). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. When the desired ...

Page 28

... REGULATOR (LDO) LF CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522 VS GND RSET REFMON DISTRIBUTION REFERENCE STATUS A/B PROGRAMMABLE PRESCALER COUNTERS N DELAY N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE ...

Page 29

... PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. Table 25. Setting the PFD Polarity Register Description 0x010[ PFD polarity positive (higher control voltage produces higher frequency) 0x010[ PFD polarity negative (higher control voltage produces lower frequency) Rev Page AD9522-3 ...

Page 30

... REGULATOR (LDO) LF CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522 VS GND RSET REFMON DISTRIBUTION REFERENCE STATUS A/B PROGRAMMABLE PRESCALER COUNTERS N DELAY N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE ...

Page 31

... Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz The AD9522 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6). This is a distribution-only mode that ...

Page 32

... RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522 Figure 39. High Frequency Clock Distribution or External VCO > 1600 MHz (Mode 2) VS GND RSET REFMON DISTRIBUTION REFERENCE STATUS A/B PROGRAMMABLE PRESCALER COUNTERS N DELAY N DIVIDER ZERO DELAY BLOCK ...

Page 33

... In addition, the PLL can be used to clean up jitter and phase noise on a noisy reference. The exact choice of PLL parameters and loop dynamics is application specific. The flexibility and depth of the AD9522 PLL allow the part to be tailored to function in many different applications and signal environments. ...

Page 34

... PUMP Figure 42. Example of External Loop Filter for a PLL Using an External VCO PLL Reference Inputs The AD9522 features a flexible PLL reference input circuit that allows a fully differential input, two separate single-ended inputs 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip maintaining amplifier. An optional reference clock doubler can be used to double the PLL reference frequency ...

Page 35

... PLL reference clock switching between REF1 (on Pin REFIN) and REF2 (on Pin REFIN ). This feature supports networking and other applications that require redundant references. The AD9522 features a dc offset option in single-ended mode. This option is designed to eliminate the risk of the reference inputs chattering when they are ac-coupled and the reference clock disappears ...

Page 36

... VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9522 B counter is bypassed (B = 1), the A counter should be set to zero, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 16, and 32 ...

Page 37

... Note that it is possible in certain low (<500 Hz) loop bandwidth, high phase margin cases that the DLD can chatter during acqui- sition, which can cause the AD9522 to automatically enter and exit holdover. To avoid this problem recommended that the user make provisions for a capacitor to ground on the LD pin so that current source digital lock detect (CSDLD) mode can be used ...

Page 38

... AD9522-3 External VCXO/VCO Clock Input (CLK/ CLK ) This differential input is used to drive the AD9522 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. CLOCK INPUT STAGE VS CLK CLK 2.5kΩ ...

Page 39

... R and N dividers for faster settling of the PLL and reduces frequency errors during settling. Because the prescaler is not reset, this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out. Rev Page AD9522-3 ...

Page 40

... Frequency Status Monitors The AD9522 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 48 ...

Page 41

... PLL locks. A SYNC is executed during the VCO calibration; therefore, the outputs of the AD9522 are held static during the calibration, which prevents unwanted frequencies from being produced. However, at the end of a VCO calibration, the outputs may resume clocking before the PLL loop is completely settled. ...

Page 42

... Figure 49. Zero Delay Function External Zero Delay Mode The external zero delay function of the AD9522 is achieved by feeding one clock output back to the CLK input and ultimately back to the PLL N divider. In Figure 49, the change in signal routing for external zero delay mode is shown in red. ...

Page 43

... The VCO divider has two purposes. The first is to limit the maximum input frequency of the channel dividers to 1.6 GHz. The other is to allow the AD9522 to generate even lower frequencies than would be possible with only a simple post divider. External clock signals connected to the CLK input can also use the VCO divider ...

Page 44

... AD9522-3 Clock Frequency Division The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the VCO or CLK to the output is the product of the VCO divider ( and 6) and the division of the channel divider. Table 32 indicates how the frequency division for a channel is set ...

Page 45

... Synchronizing the Outputs— Function section). Table 38. Setting Phase Offset and Division Start Divider High (SH) 0 0x191[4] 1 0x194[4] 2 0x197[4] 3 0x19A[4] Rev Page AD9522-3 D Output Duty Cycle X Disable Div DCC = 1 Disable Div DCC = 1)/ 50%, requires 1)/ 50%, requires 1 X%)/(2 × 3), ...

Page 46

... There is an uncertainty one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9522. The pipeline delay from the SYNC rising edge to the beginning of the synchronized output clocking is between 14 cycles and ...

Page 47

... CHANNEL DIVIDER Figure 53. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used—CLK Input Only LVDS Output Drivers The AD9522 output drivers can be configured as either an LVDS differential output pair of CMOS single-ended outputs. The LVDS outputs allow for selectable output current from ~1 ...

Page 48

... Because this is not a complete power-down, it can be called sleep mode. The AD9522 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode. When the AD9522 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). ...

Page 49

... PLL Power-Down The PLL section of the AD9522 can be selectively powered down. There are two PLL power-down modes set by Register 0x010[1:0]: asynchronous and synchronous. In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps ...

Page 50

... The AD9522 supports both I2C protocols: standard mode (100 kHz) and fast mode (400 kHz). The AD9522 I2C port has a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL I2C bus system, the AD9522 is connected to the serial bus (data bus SDA and clock bus SCL slave device, meaning that no clock is generated by the AD9522 ...

Page 51

... A repeated start (Sr) condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. Rev Page AD9522-3 ACKNOWLEDGE FROM SLAVE-RECEIVER ...

Page 52

... AD9522-3 Data Transfer Format Send byte format—the send byte protocol is used to set up the register address for subsequent commands. S Slave Address W A Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address. ...

Page 53

... SDO). By default, the AD9522 is in bidirectional mode. Short instruction mode (8-bit instructions) is not supported. Only long (16-bit) instruction mode is supported. A write or a read operation to the AD9522 is initiated by pulling CS low. The CS stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred ...

Page 54

... In MSB first mode, subsequent bytes increment the address. SPI MSB/LSB FIRST TRANSFERS The AD9522 instruction word and byte data can be MSB first or LSB first. Any data written to 0x000 must be mirrored; the upper four bits ([7:4]) must mirror the lower four bits ([3:0]). ...

Page 55

... Figure 67. Timing Diagram for Serial Control Port Register Read A9 A10 A11 A12 REGISTER (N) DATA Rev Page REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA t C DON'T CARE DON'T CARE REGISTER ( DATA AD9522-3 LSB I0 A0 DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE ...

Page 56

... AD9522 SCLK SDIO Table 45. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) ...

Page 57

... In I2C mode, the user can address the AD9522 slave port with the external I2C master (send an address byte to the AD9522). If the AD9522 responds with a no acknowledge bit, the data transfer process is not done. If the AD9522 responds with an acknowledge bit, the data transfer process is completed ...

Page 58

... Instead, the default power-up values for the EEPROM buffer segment allow the user to store all of the AD9522 register values from Register 0x000 to Register 0x231 to the EEPROM. For example, if users want to load only the output driver settings ...

Page 59

... Address [15:8] of the second group of registers Address [7:0] of the second group of registers Number of bytes [6:0] of the third group of registers Address [15:8] of the third group of registers Address [7:0] of the third group of registers IO_UPDATE operational code (0x80) End-of-data operational code (0xFF) Rev Page AD9522-3 Bit 2 Bit 1 Bit 0 (LSB) ...

Page 60

... Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 JC Ψ Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) JT The AD9522 is specified for a case temperature (T that T is not exceeded, an airflow source can be used. CASE Use the following equation to determine the junction ...

Page 61

... A counter 13-bit B counter, Bits[12:8] (MSB) Prescaler P Antibacklash pulse width VCO calibration divider VCO calibration now N path delay LD pin control REFMON pin control Enable Enable Enable REF2 REF1 differential reference Unused Enable Enable external holdover holdover AD9522-3 Default Value (Hex N/A N/A N ...

Page 62

... AD9522-3 Addr (Hex) Parameter Bit 7 (MSB) 01E PLL_CTRL_9 01F PLL_Readback Unused (read-only) Output Driver Control 0F0 OUT0 control OUT0 format 0F1 OUT1 control OUT1 format 0F2 OUT2 control OUT2 format 0F3 OUT3 control OUT3 format 0F4 OUT4 control OUT4 format 0F5 ...

Page 63

... Unused Disable power-on SYNC Unused Unused Unused EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1) EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2) Rev Page AD9522-3 Bit 2 Bit 1 Bit 0 (LSB) Divider 1 high cycles Divider 1 phase offset Channel 1 Reserved Disable ...

Page 64

... AD9522-3 Addr (Hex) Parameter Bit 7 (MSB) A05 EEPROM EEPROM Buffer Segment Register 6 (default: Bits[7:0] of starting register address for Group 2) Buffer Segment Register 6 A06 EEPROM 0 Buffer Segment Register 7 A07 EEPROM EEPROM Buffer Segment Register 8 (default: Bits[15:8] of starting register address for Group 3) Buffer Segment ...

Page 65

... EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2 Bit 6 Bit 5 Bit 4 Bit 3 Unused Unused Unused Unused Rev Page AD9522-3 Bit 2 Bit 1 Bit 0 (LSB) Unused STATUS_ EEPROM Unused EEPROM data error Soft_EEPROM Enable (self-clearing) EEPROM write Unused REG2EEPROM (self-clearing) Default ...

Page 66

... EEPROM. It does not affect AD9522 operation in any way (default: 0x00). 16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a unique ID to identify which version of the AD9522 register settings is stored in the EEPROM. It does not affect AD9522 operation in any way (default: 0x00). ...

Page 67

... Charge Pump Mode High impedance state. Force source current (pump up). Force sink current (pump down). Normal operation (default). Mode Normal operation; this mode must be selected to use the PLL. Asynchronous power-down (default). Unused. Synchronous power-down. Rev Page AD9522-3 ...

Page 68

... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description 016 [3] B counter B counter bypass. This is only valid when operating the prescaler in FD mode. bypass [ normal (default). [ counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. 016 [2:0] Prescaler P Prescaler dual modulus and FD = fixed divide ...

Page 69

... Selected reference (low = REF2, high = REF1 LVL DLD (active low LVL Holdover active (active low LVL LD pin comparator output (active low). Antibacklash Pulse Width (ns) 2.9 (default) 1.3 6.0 2.9 PFD Cycles to Determine Lock 5 (default 255 VCO Calibration Clock Divider (default) Rev Page AD9522-3 ...

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... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description 018 [0] VCO calibration Bit used to initiate the VCO calibration. This bit must be toggled from the active registers. The now sequence to initiate a calibration follows: program to 0, followed by an IO_UPDATE bit (Register 0x232[0]); then program to 1, followed by another IO_UPDATE bit (Register 0x232[0]). This sequence gives complete control over when the VCO calibration occurs relative to the programming of other registers that can impact the calibration (default = 0) ...

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... Status REF2 frequency (active high LVL (Status REF1 frequency) AND (status REF2 frequency LVL (DLD) AND (status of selected reference) AND (status of VCO LVL Status of VCO frequency (active high LVL Selected reference (low = REF1, high = REF2 LVL DLD; active low. Rev Page AD9522-3 ...

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... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description [4] [ 01C [7] Disable Disables or enables the switchover deglitch circuit. switchover [ enable the switchover deglitch circuit (default). deglitch [ disable the switchover deglitch circuit. 01C [6] Select REF2 If Register 0x01C[ selects the reference for PLL when in manual; register selected reference control. ...

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... Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode. comparator When the AD9522 is in internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 47). Otherwise, this can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin. [ ...

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... AD9522-3 Reg. Addr (Hex) Bit(s) Name Description 01F [2] REF2 frequency Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency > threshold set by Register 0x01A[6]. (read-only) [ REF2 frequency is less than the threshold frequency. [ REF2 frequency is greater than the threshold frequency. ...

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... SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [ divider output forced to low (default). [ divider output forced to high. Selects clock output to start high or start low. [ start low (default). [ start high. Phase offset (default: 0x0). Rev Page AD9522-3 ...

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... AD9522-3 Reg. Addr (Hex) Bit(s) Name 192 [2] Channel 0 power-down 192 [0] Disable Divider 0 DCC 193 [7:4] Divider 1 low cycles 193 [3:0] Divider 1 high cycles 194 [7] Divider 1 bypass 194 [6] Divider 1 ignore SYNC 194 [5] Divider 1 force high 194 [4] Divider 1 start high 194 [3:0] Divider 1 phase offset ...

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... OUT10/OUT10, and OUT11/OUT11 are put into the high impedance power-down mode by setting this bit.) Duty-cycle correction function. [ enable duty-cycle correction (default). [ disable duty-cycle correction. Description [2] [ normal operation (default). [ power down. Rev Page AD9522-3 Divide 2 (default Output static 1 (bypass) Output static ...

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... AD9522-3 Reg. Addr (Hex) Bit(s) Name 1E1 [3] Power-down VCO clock interface Powers down the interface block between VCO and clock distribution. 1E1 [2] Power-down VCO and CLK 1E1 [1] Select VCO or CLK 1E1 [0] Bypass VCO divider Table 56. System Reg. Addr (Hex) Bit(s) Name ...

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... EEPROM. Because the AD9522 register space is noncontiguous, to EEPROM Buffer the EEPROM controller needs to know the starting address and number of bytes in the AD9522 register Segment Register 23 space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM buffer segment ...

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... USING THE AD9522 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock of the AD9522. An ADC can be thought sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to- digital output ...

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... See the AN-586 Application Note at www.analog.com information on LVDS. CMOS CLOCK DISTRIBUTION The output drivers of the AD9522 can be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as inverting or noninverting. These outputs are 3 ...

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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range AD9522-3BCPZ 1 −40°C to +85°C 1 AD9522-3BCPZ-REEL7 −40°C to +85°C 1 AD9522-3/PCBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ ...

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... NOTES Rev Page AD9522-3 ...

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... AD9522-3 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07224-0-10/08(0) Rev Page ...

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