AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet

12- Channel Clock Generator With Integra

AD9522-5BCPZ

Manufacturer Part Number
AD9522-5BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet

Specifications of AD9522-5BCPZ

Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
800MHz
Ic Interface Type
I2C, SPI
Frequency
2.4GHz
No. Of Outputs
12
No. Of Multipliers / Dividers
4
Supply Voltage Range
3.135V To 3.465V
Digital Ic Case Style
LFCSP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9522-5BCPZ
Manufacturer:
Analog Devices Inc.
Quantity:
316
Part Number:
AD9522-5BCPZ-REEL7
Manufacturer:
Analog Devices Inc.
Quantity:
320
FEATURES
Low phase noise, phase-locked loop (PLL)
Twelve 800 MHz LVDS outputs divided into 4 groups
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9522-5
with subpicosecond jitter performance, along with an on-chip PLL
that can be used with an external VCO.
1
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific
member of the AD9522 family.
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVPECL, or LVDS references to 250 MHz
Accepts 16.62 MHz to 33.33 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Each group of 3 has a 1-to-32 divider with phase delay
Additive broadband jitter as low as 242 fs rms
Channel-to-channel skew grouped outputs < 60 ps
Each LVDS output can be configured as 2 CMOS outputs
and other 10 Gbps protocols
with selectable revertive/nonrevertive switching
(for f
OUT
≤ 250 MHz)
1
provides a multioutput clock distribution function
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The AD9522 serial interface supports both SPI and I2C® ports.
An in-package EEPROM can be programmed through the
serial interface and store user-defined register settings for
power-up and chip reset.
The AD9522 features 12 LVDS outputs in four groups. Any of
the 800 MHz LVDS outputs can be reconfigured as two
250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide
ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9522 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage up to 5.5 V.
The AD9522 is specified for operation over the standard industrial
range of −40°C to +85°C.
The
LVPECL/CMOS drivers instead of LVDS/CMOS drivers.
REFIN
REFIN
CLK
AD9520-5
12 LVDS/24 CMOS Output
FUNCTIONAL BLOCK DIAGRAM
SPI/I
DIGITAL LOGIC
REF1
REF2
PORT AND
is an equivalent part to the AD9522-5 featuring
2
C CONTROL
AND MUXES
©2008 Analog Devices, Inc. All rights reserved.
DIVIDER
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
CP
EEPROM
Figure 1.
Clock Generator
LVDS/
CMOS
AD9522-5
MONITOR
AD9522-5
STATUS
DELAY
ZERO
www.analog.com
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11

AD9522-5BCPZ Summary of contents

Page 1

... PLL that can be used with an external VCO. 1 The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used referring to that specific member of the AD9522 family. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...

Page 2

... AD9522-5 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 7 Clock Outputs ............................................................................... 7 Timing Characteristics ................................................................ 8 Timing Diagrams ..................................................................... 8 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 9 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ...

Page 3

... Thermal Performance ..................................................................... 54   Register Map .................................................................................... 55   Register Map Descriptions ............................................................. 60   Applications Information ............................................................... 73   Frequency Planning Using the AD9522 .................................. 73   Using the AD9522 Outputs for ADC Clock Applications .... 73   LVDS Clock Distribution ........................................................... 73   CMOS Clock Distribution ......................................................... 74   Outline Dimensions ........................................................................ 75   Ordering Guide ........................................................................... 75   ...

Page 4

... AD9522-5 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5. (min) and maximum (max) values are given over full VS and T POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ VS 3.135 3.3 VCP VS RSET Pin Resistor 4.12 CPRSET Pin Resistor 5.1 PLL CHARACTERISTICS Table 2 ...

Page 5

... REF refers to REFIN (REF1)/REFIN (REF2) 1890 2348 3026 ps When N delay and R delay are bypassed 900 1217 1695 ps When N delay = Setting 111 and R delay is bypassed Rev Page AD9522-5 is possible by changing CP is possible by changing < VCP − 0 the voltage on the CP (charge CP CP < VCP − 0.5 V ...

Page 6

... AD9522-5 Parameter NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit (FOM) 2 PLL DIGITAL LOCK DETECT WINDOW Lock Threshold (Coincidence of Edges) Low Range (ABP 1 ...

Page 7

... V 0.5 V Rev Page AD9522-5 Test Conditions/Comments Termination = 100 Ω across differential pair Differential (OUT, OUT) The AD9522 outputs toggle at higher frequencies, but the output amplitude may not meet the V specification V − V measurement across a differential pair the default amplitude setting with output driver not toggling ...

Page 8

... AD9522-5 TIMING CHARACTERISTICS Table 5. Parameter LVDS OUTPUT RISE/FALL TIMES Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVDS OUTPUT LVDS For All Divide Values Variation with Temperature 1 OUTPUT SKEW, LVDS OUTPUTS LVDS Outputs That Share the Same Divider LVDS Outputs on Different Dividers ...

Page 9

... Input slew rate > 1 V/ns −102 dBc/Hz −114 dBc/Hz −122 dBc/Hz −129 dBc/Hz −135 dBc/Hz −140 dBc/Hz −150 dBc/Hz Input slew rate > 1 V/ns −125 dBc/Hz −136 dBc/Hz −144 dBc/Hz −152 dBc/Hz −157 dBc/Hz −160 dBc/Hz −164 dBc/Hz Rev Page AD9522-5 ...

Page 10

... AD9522-5 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 7. Parameter LVDS OUTPUT ABSOLUTE TIME JITTER LVDS = 245.76 MHz; PLL LBW = 125 Hz LVDS = 122.88 MHz; PLL LBW = 125 Hz LVDS = 61.44 MHz; PLL LBW = 125 Hz CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 8 ...

Page 11

... CS has an internal 30 kΩ pull-up resistor 2 μA −110 μA The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor 2 pF SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I 2.0 V 0.8 V 110 μ ...

Page 12

... AD9522-5 SERIAL CONTROL PORT—I²C MODE Table 11. Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 × VS and 0.9 × VS Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by ...

Page 13

... Test Conditions/Comments Each of these pins has an internal 30 kΩ pull-up resistor 2 μA −110 μA The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor 100 ns 1.3 ns High speed clock is CLK input signal Unit ...

Page 14

... AD9522-5 POWER DISSIPATION Table 15. Parameter POWER DISSIPATION, CHIP Power-On Default Distribution Only Mode; VCO Divider On; One LVDS Output Enabled Distribution Only Mode; VCO Divider Off; One LVDS Output Enabled Maximum Power, Full Operation PD Power-Down PD Power-Down, Maximum Sleep VCP Supply POWER DELTAS, INDIVIDUAL FUNCTIONS ...

Page 15

... 0.3 V JESD51-2. See the Thermal Performance section for more details. −0 0.3 V Table 17. Package Type 64-Lead LFCSP (CP-64-4) −0 0.3 V ESD CAUTION −0 0.3 V −0 0.3 V 150°C −65°C to +150°C 300°C Rev Page AD9522-5 θ Unit JA 22 °C/W ...

Page 16

... I CLK Differential clock input 14 I Differential CLK clock input VS 1 PIN 1 INDICATOR VCP AD9522-5 8 TOP VIEW NC 9 (Not to Scale CLK 13 CLK Figure 5. Pin Configuration Description 3.3 V Power Pins. Reference Monitor (Output). This pin has multiple selectable outputs. Lock Detect (Output). This pin has multiple selectable outputs. ...

Page 17

... Three-level logic. This pin is internally biased for the open logic level. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9522 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 kΩ ...

Page 18

... AD9522-5 Input/ Pin Pin No. Output Type Mnemonic 47 O LVDS or OUT3 (OUT3B) CMOS 48 O OUT3 (OUT3A) LVDS or CMOS 50 O LVDS or OUT2 (OUT2B) CMOS 51 O LVDS or OUT2 (OUT2A) CMOS 52 O LVDS or OUT1 (OUT1B) CMOS 53 O LVDS or OUT1 (OUT1A) CMOS 55 O LVDS or OUT0 (OUT0B) ...

Page 19

... PUMP DOWN PUMP 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOLTAGE ON CP PIN (V) Figure 9. Charge Pump Characteristics @ VCP = 5 PFD FREQUENCY (MHz) DIFFERENTIAL INPUT SINGLE-ENDED INPUT 0 0.2 0.4 0.6 0.8 1.0 INPUT SLEW RATE (V/ns) AD9522-5 4 100 1.2 1.4 ...

Page 20

... AD9522-5 3.5 VS_DRV = 3.3V 3.0 VS_DRV = 3.135V 2.5 VS_DRV = 2.5V VS_DRV = 2.35V 2.0 1.5 1.0 0.5 0 10k 1k RESISTIVE LOAD (Ω) Figure 12. CMOS Output V (Static) vs 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0 TIME (ns) Figure 13. LVDS Output (Differential) @ 100 MHz, Output Terminated 100 Ω Across Differential Pair ...

Page 21

... Rev Page AD9522-5 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 21. Additive (Residual) Phase Noise, CLK-to-LVDS @ 800 MHz, Divide-by-1 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 22. Additive (Residual) Phase Noise, ...

Page 22

... AD9522-5 –80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs –90 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 24. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz 10M 100M Rev Page ...

Page 23

... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9522-5 ...

Page 24

... AMP CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522-5 VS GND RSET REFMON DISTRIBUTION REFERENCE STATUS PROGRAMMABLE A/B N DELAY PRESCALER COUNTERS N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE BY ...

Page 25

... THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9522 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 43 to Table 54). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. When the desired ...

Page 26

... AMP CLK CLK PD DIGITAL EEPROM SYNC LOGIC RESET EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522-5 VS GND RSET REFMON DISTRIBUTION REFERENCE STATUS PROGRAMMABLE A/B N DELAY PRESCALER COUNTERS N DIVIDER ZERO DELAY BLOCK DIVIDE DIVIDE DIVIDE DIVIDE BY ...

Page 27

... Mode 2: High Frequency Clock Distribution—CLK or External VCO > 1600 MHz The AD9522 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/ CLK input is connected to the distribution section through the VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/ divide-by-5/divide-by-6). This is a distribution-only mode that ...

Page 28

... EEPROM SERIAL SP1 PORT SP0 DECODE 2 SPI I C INTERFACE INTERFACE SCLK/SCL SDIO/SDA SDO CS AD9522-5 Figure 27. High Frequency Clock Distribution—CLK or External VCO > 1600 MHz (Mode 2) VS GND RSET REFMON DISTRIBUTION REFERENCE STATUS PROGRAMMABLE A/B N DELAY PRESCALER COUNTERS N DIVIDER ZERO DELAY BLOCK ...

Page 29

... In addition, the PLL can be used to clean up jitter and phase noise on a noisy reference. The exact choice of PLL parameters and loop dynamics is application specific. The flexibility and depth of the AD9522 PLL allow the part to be tailored to function in many different applications and signal environments. ...

Page 30

... When using the reference switchover, the single-ended reference inputs should be dc-coupled CMOS levels (with the AD9522 dc offset feature disabled). Alternatively, the inputs can be ac-coupled, and the dc offset feature can be enabled. The user should keep in mind, however, that the minimum input amplitude for the reference inputs is greater when the dc offset is turned on ...

Page 31

... VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9522 B counter is bypassed (B = 1), the A counter should be set to zero, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 16, and 32 ...

Page 32

... DM 13 130 DM Analog Lock Detect (ALD) The AD9522 provides an ALD function that can be selected for use at the LD pin. There are two operating modes for ALD. • N-channel open-drain lock detect. This signal requires a pull-up resistor to the positive supply, VS. The output is normally high with short, low going pulses. Lock is indicated by the minimum duty cycle of the low going pulses. • ...

Page 33

... STATUS Figure 32. Current Source Digital Lock Detect External VCXO/VCO Clock Input (CLK/ CLK ) This differential input is used to drive the AD9522 clock distribution section. This input can receive up to 2.4 GHz. The pins are internally self-biased, and the input signal should be ac-coupled via capacitors. ...

Page 34

... AD9522-5 PLL ENABLED DLD == LOW YES WAS LD PIN == HIGH WHEN DLD WENT LOW? YES HIGH IMPEDANCE CHARGE PUMP REFERENCE EDGE AT PFD? YES RELEASE CHARGE PUMP HIGH IMPEDANCE DLD == HIGH Automatic/Internal Holdover Mode When enabled, the automatic/internal holdover mode auto- matically puts the charge pump into a high impedance state when the loop loses lock ...

Page 35

... Frequency Status Monitors The AD9522 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. Figure diagram that shows their location in the PLL ...

Page 36

... AD9522-5 REF_SEL REFERENCE SWITCHOVER REF1 STATUS REF2 OPTIONAL STATUS REFIN BUF REFIN CLK CLK VS GND RSET REFMON DISTRIBUTION REFERENCE CLK FREQUENCY STATUS A/B PROGRAMMABLE N DELAY PRESCALER COUNTERS N DIVIDER ZERO DELAY BLOCK DIVIDE FROM CHANNEL DIVIDER Figure 35. Reference and CLK Frequency Status Monitors Rev ...

Page 37

... Zero delay operation aligns the phase of the output clocks with the phase of the external PLL reference input. The zero delay function of the AD9522-5 is achieved by feeding the output of Channel Divider 0 back to the PLL N divider. In Figure 36, the change in signal routing for zero delay mode is shown in blue ...

Page 38

... The VCO divider has two purposes. The first is to limit the maximum input frequency of the channel dividers to 1.6 GHz. The other is to allow the AD9522 to generate even lower frequencies than would be possible with only a simple post divider. The channel dividers allow for a selection of various duty cycles, depending on the currently set division ...

Page 39

... Disable Divider Bypass Div DCC Even 0x191[7] 0x192[0] 0x194[7] 0x195[0] Odd = 3 0x197[7] 0x198[0] 0x19A[7] 0x19B[0] Odd = 5 Even, odd Even, odd Rev Page AD9522 This allows X D Output Duty Cycle X Disable Div Disable Div DCC = 1 DCC = 0 Channel 50% 50% divider bypassed Channel 33.3% ...

Page 40

... AD9522-5 Table 30. Channel Divider Output Duty Cycle with VCO Divider ≠ 1, Input Duty Cycle Output Duty Cycle X VCO Disable Div Divider DCC = 1 Disable Div DCC = 0 Even Channel 50% 50% divider bypassed Odd = 3 Channel 33. X%)/3 divider bypassed Odd = 5 Channel 40 X%)/5 divider bypassed Even ...

Page 41

... There is an uncertainty one cycle of the clock at the input to the channel divider due to the asynchronous nature the SYNC signal with respect to the clock edges inside the AD9522. The pipeline delay from the SYNC rising edge to the beginning of the synchronized output clocking is between 14 cycles and ...

Page 42

... OUTPUT OF CHANNEL DIVIDER Figure 40. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used LVDS Output Drivers The AD9522 output drivers can be configured as either an LVDS differential output pair of CMOS single-ended outputs. The LVDS outputs allow for selectable output current from ~1. mA. ...

Page 43

... Because this is not a complete power-down, it can be called sleep mode. The AD9522 contains special circuitry to prevent runt pulses on the outputs when the chip is entering or exiting sleep mode. When the AD9522 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). ...

Page 44

... AD9522-5 PLL Power-Down The PLL section of the AD9522 can be selectively powered down. There are two PLL power-down modes set by Register 0x010[1:0]: asynchronous and synchronous. In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps ...

Page 45

... The AD9522 I2C port has a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL I2C bus system, the AD9522 is connected to the serial bus (data bus SDA and clock bus SCL slave device, meaning that no clock is generated by the AD9522. The AD9522 uses direct 16-bit (two bytes) memory addressing instead of traditional 8-bit (one byte) memory addressing ...

Page 46

... AD9522-5 SDA MSB SCL SDA MSB = 0 SCL Figure 46. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration) MSB = 1 SDA SCL Figure 47. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration) The no acknowledge bit is the ninth bit attached to any 8-bit data byte ...

Page 47

... SET; STR HIGH Sr Figure 48. I²C Serial Port Timing Rev Page RAM Address Low Byte A RAM Data 1 A RAM Data 2 A RAM Data 2 RAM RAM R A Data 0 A Data RISE SPIKE t t IDLE HLD; STR t SET; STP P AD9522 RAM A Data ...

Page 48

... SDO). By default, the AD9522 is in bidirectional mode. Short instruction mode (8-bit instructions) is not supported. Only long (16-bit) instruction mode is supported. A write or a read operation to the AD9522 is initiated by pulling CS low. The CS stalled high mode is supported in data transfers where three or fewer bytes of data (plus instruction data) are transferred ...

Page 49

... In MSB first mode, subsequent bytes increment the address. SPI MSB/LSB FIRST TRANSFERS The AD9522 instruction word and byte data can be MSB first or LSB first. Any data written to 0x000 must be mirrored; the upper four bits ([7:4]) must mirror the lower four bits ([3:0]). ...

Page 50

... AD9522-5 Table 39. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 R A12 = 0 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 51. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data ...

Page 51

... Minimum period that SCLK should logic high state HIGH t Minimum period that SCLK should logic low state LOW t SCLK to valid SDIO and SDO (see Figure 54 CLK t t HIGH LOW t DH BIT N BIT Figure 56. Serial Control Port Timing—Write Rev Page AD9522 ...

Page 52

... In I2C mode, the user can address the AD9522 slave port with the external I2C master (send an address byte to the AD9522). If the AD9522 responds with a no acknowledge bit, the data transfer process is not done. If the AD9522 responds with an acknowledge bit, the data transfer process is completed ...

Page 53

... If this operational code is absent during a write to the EEPROM, the register values loaded from the EEPROM are not transferred to the active register space, and these values do not take effect after they are loaded from the EEPROM to the AD9522. Table 41. Example of EEPROM Buffer Segment Reg Addr (Hex) ...

Page 54

... Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD-883, Method 1012.1 JC Ψ Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) JT The AD9522 is specified for a case temperature (T that T is not exceeded, an airflow source can be used. CASE Use the following equation to determine the junction ...

Page 55

... PLL power-down 6-bit A counter 13-bit B counter, Bits[12:8] (MSB) Prescaler P Antibacklash pulse width Unused N path delay LD pin control REFMON pin control Enable Enable Enable REF2 REF1 differential reference Unused Enable Enable external holdover holdover AD9522-5 Default Value (Hex N/A N/A N ...

Page 56

... AD9522-5 Addr (Hex) Parameter Bit 7 (MSB) 01E PLL_CTRL_9 01F PLL_Readback Unused (read-only) Output Driver Control 0F0 OUT0 control OUT0 format 0F1 OUT1 control OUT1 format 0F2 OUT2 control OUT2 format 0F3 OUT3 control OUT3 format 0F4 OUT4 control OUT4 format 0F5 ...

Page 57

... Unused Disable power-on SYNC Unused Unused Unused EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1) EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2) Rev Page AD9522-5 Bit 2 Bit 1 Bit 0 (LSB) Divider 1 high cycles Divider 1 phase offset Channel 1 Reserved Disable ...

Page 58

... AD9522-5 Addr (Hex) Parameter Bit 7 (MSB) A05 EEPROM EEPROM Buffer Segment Register 6 (default: Bits[7:0] of starting register address for Group 2) Buffer Segment Register 6 A06 EEPROM 0 Buffer Segment Register 7 A07 EEPROM EEPROM Buffer Segment Register 8 (default: Bits[15:8] of starting register address for Group 3) Buffer Segment ...

Page 59

... B01 EEPROM error checking (read-only) B02 EEPROM Control 1 B03 EEPROM Control 2 Bit 6 Bit 5 Bit 4 Bit 3 Unused Unused Unused Unused Rev Page AD9522-5 Bit 2 Bit 1 Bit 0 (LSB) STATUS_ EEPROM EEPROM data error Soft_EEPROM Enable (self-clearing) EEPROM write REG2EEPROM (self-clearing) Default Value (Hex) 00 ...

Page 60

... EEPROM. It does not affect AD9522 operation in any way (default: 0x00). 16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a unique ID to identify which version of the AD9522 register settings is stored in the EEPROM. It does not affect AD9522 operation in any way (default: 0x00). ...

Page 61

... Charge Pump Mode High impedance state. Force source current (pump up). Force sink current (pump down). Normal operation (default). Mode Normal operation; this mode must be selected to use the PLL. Asynchronous power-down (default). Unused. Synchronous power-down. Rev Page AD9522-5 ...

Page 62

... AD9522-5 Reg. Addr (Hex) Bit(s) Name Description 016 [3] B counter B counter bypass. This is valid only when operating the prescaler in FD mode. bypass [ normal (default). [ counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. 016 [2:0] Prescaler P Prescaler dual modulus and FD = fixed divide ...

Page 63

... Status of REF2 frequency (active low). (Status of REF1 frequency) AND (status of REF2 frequency). (DLD) AND (Status of selected reference) AND (status of VCO). Status of CLK frequency (active low). Selected reference (low = REF2, high = REF1). DLD (active low). Holdover active (active low). LD pin comparator output (active low). AD9522-5 ...

Page 64

... AD9522-5 Reg. Addr (Hex) Bit(s) Name Description 01A [7] Enable STATUS Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the pin divider R and N dividers. [ divide-by-4 disabled on STATUS pin (default). [ divide-by-4 enabled on STATUS pin. 01A [6] Ref freq monitor Sets the reference (REF1/REF2) frequency monitor’ ...

Page 65

... LD pin comparator output (active high LVL VS (PLL supply DYN REF1 clock (differential reference when in differential mode DYN REF2 clock (not available in differential mode DYN Selected reference to PLL (differential reference when in differential mode DYN Unselected reference to PLL (not available when in differential mode). Rev Page AD9522-5 ...

Page 66

... AD9522-5 Reg. Addr (Hex) Bit(s) Name Description [4] [ 01C [7] Disable Disables or enables the switchover deglitch circuit. switchover [ enable the switchover deglitch circuit (default). deglitch [ disable the switchover deglitch circuit. 01C [6] Select REF2 If Register 0x01C[ selects the reference for PLL when in manual; register selected reference control. ...

Page 67

... Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode. comparator When the AD9522 is in internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 34). Otherwise, this can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin. [ ...

Page 68

... AD9522-5 Table 48. Output Driver Control Reg. Addr (Hex) Bit(s) Name Description 0F0 [7] OUT0 format Selects the output type for OUT0. [ LVDS (default). [ CMOS. 0F0 [6:5] OUT0 CMOS Sets the CMOS output configuration for OUT0 when 0x0F0[ configuration [6: (default) 0F0 [4:3] OUT0 polarity Sets the output polarity for OUT0 ...

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... Bypasses and powers down the divider; routes input to divider output. [ use divider (default). [ bypass divider. Ignore SYNC. [ obey chip-level SYNC signal (default). [ ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [ divider output forced to low (default). [ divider output forced to high. Rev Page AD9522-5 ...

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... AD9522-5 Reg. Addr (Hex) Bit(s) Name 194 [4] Divider 1 start high 194 [3:0] Divider 1 phase offset 195 [2] Channel 1 power-down 195 [0] Disable Divider 1 DCC 196 [7:4] Divider 2 low cycles 196 [3:0] Divider 2 high cycles 197 [7] Divider 2 bypass 197 [6] Divider 2 ignore SYNC 197 [5] Divider 2 force high ...

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... The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed; that is, a high level forces the selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. [ same as SYNC high. [ same as SYNC low. Rev Page AD9522-5 Divide 2 (default ...

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... EEPROM. Because the AD9522 register space is noncontiguous, to EEPROM Buffer the EEPROM controller needs to know the starting address and number of bytes in the AD9522 register Segment Register 23 space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM buffer segment ...

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... USING THE AD9522 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of the sampling clock of the AD9522. An ADC can be thought sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to- digital output ...

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... MICROSTRIP Figure 59. Series Termination of CMOS Output Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9522 do not supply enough current to provide a full voltage swing with a low impedance resistive, far- end termination, as shown in Figure 60. The far-end termination network should match the PCB trace impedance and provide the desired switching point ...

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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range AD9522-5BCPZ 1 −40°C to +85°C 1 AD9522-5BCPZ-REEL7 −40°C to +85°C 1 AD9522-5/PCBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ ...

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... AD9522-5 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07240-0-12/08(0) Rev Page ...

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