AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 12

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
SERIAL CONTROL PORT—I²C MODE
Table 11.
Parameter
SDA, SCL (WHEN INPUTTING DATA)
SDA (WHEN OUTPUTTING DATA)
TIMING
1
According to the original I
falling edge.
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be Suppressed by
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIH
Clock Rate (SCL, f
Bus Free Time Between a Stop and Start Condition, t
Setup Time for a Repeated Start Condition, t
Hold Time (Repeated) Start Condition (After This Period,
Setup Time for Stop Condition, t
Low Period of the SCL Clock, t
High Period of the SCL Clock, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Capacitive Load for Each Bus Line, C
0.1 × VS and 0.9 × VS
the Input Filter, t
Capacitance from 10 pF to 400 pF
the First Clock Pulse Is Generated), t
I2C
HLD; DAT
SET; DAT
SPIKE
)
FALL
2
RISE
C specification, an I
MIN
to VIL
LOW
HIGH
SET; STP
MAX
b
2
C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
with a Bus
HLD; STR
SET; STR
IDLE
Rev. 0 | Page 12 of 76
Min
0.7 × VS
−10
0.015 × VS
20 + 0.1 C
1.3
0.6
0.6
0.6
1.3
0.6
20 + 0.1 C
20 + 0.1 C
120
140
b
b
b
Typ
Max
0.3 × VS
+10
50
0.4
250
400
300
300
880
400
Unit
ns
kHz
μs
μs
μs
μs
μs
μs
pF
V
V
μA
V
V
ns
ns
ns
ns
ns
Test Conditions/Comments
C
Note that all I
to VIH
(0.7 × VS)
C
C
This is a minor deviation from the
original I²C specification of 100 ns
minimum
This is a minor deviation from the
original I²C specification of 0 ns
minimum
b
b
b
= capacitance of one bus line in pF
= capacitance of one bus line in pF
= capacitance of one bus line in pF
MIN
(0.3 × VS) and VIL
1
2
C timing values refer
MAX
levels