AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 60

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
REGISTER MAP DESCRIPTIONS
Table 44 through Table 54 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. Reference to a specific bit or range of bits within a register is indicated by squared brackets. For example, [3] refers to Bit 3 and
[5:2] refers to the range of bits from Bit 5 through Bit 2.
Table 44. SPI Mode Serial Port Configuration
Reg Addr (Hex)
000
000
000
000
000
004
Table 45. I
Reg Addr (Hex)
000
000
000
000
004
Table 46. EEPROM ID
Reg Addr (Hex)
005
006
2
C Mode Serial Port Configuration
Bit(s)
[7]
[6]
[5]
[4]
[3:0]
[0]
Bit(s)
[7:0]
[7:0]
Bit(s)
[7:6]
[5]
[4]
[3:0]
[0]
Name
SDO active
LSB first/addr incr
Soft reset
Unused
Mirror[7:4]
Readback active registers
Name
EEPROM customer
version ID (LSB)
EEPROM customer
version ID (MSB)
Name
Unused
Soft reset
Unused
Mirror[7:4]
Readback active registers
Description
Selects unidirectional or bidirectional data transfer mode.
[7] = 0; SDIO pin used for write and read; SDO is high impedance (default).
[7] = 1; SDO used for read; SDIO used for write; unidirectional mode.
SPI MSB or LSB data orientation. (This register is ignored in I
[6] = 0; data-oriented MSB first; addressing decrements (default).
[6] = 1; data-oriented LSB first; addressing increments.
Soft reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit
self-clears on the next SCLK cycle after the completion of writing to this register.
Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part
is in MSB or LSB first mode (see Register 0x000[6]). Set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
Select register bank used for a readback.
[0] = 0; read back buffer registers (default).
[0] = 1; read back active registers.
Description
Soft reset.
[5] = 1 (self-clearing). Soft reset; restores default values to internal registers. This bit
self-clears on the next SCL cycle after the completion of writing to this register.
Bits[3:0] should always mirror Bits[7:4]. Set bits as follows:
[0] = [7]
[1] = [6]
[2] = [5]
[3] = [4]
Select register bank used for a readback.
[0] = 0; read back buffer registers (default).
[0] = 1; read back active registers.
16-bit EEPROM ID[7:0]. This register, along with 0x006, allows the user to store a
unique ID to identify which version of the AD9522 register settings is stored in the
EEPROM. It does not affect AD9522 operation in any way (default: 0x00).
16-bit EEPROM ID[15:8]. This register, along with 0x005, allows the user to store a
unique ID to identify which version of the AD9522 register settings is stored in the
EEPROM. It does not affect AD9522 operation in any way (default: 0x00).
Description
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2
C mode.)