AD9522-5BCPZ-REEL7 Analog Devices Inc, AD9522-5BCPZ-REEL7 Datasheet - Page 72
![12- Channel Clock Generator With Integra](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9522-5BCPZ-REEL7
Manufacturer Part Number
AD9522-5BCPZ-REEL7
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-5BCPZ-REEL7.pdf
(76 pages)
Specifications of AD9522-5BCPZ-REEL7
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
800MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9522-5
Table 52. Update All Registers
Reg.
Addr
(Hex) Bit(s) Name
232
Table 53. EEPROM Buffer Segment
Reg.
Addr
(Hex) Bit(s) Name
A00 to
A16
Table 54. EEPROM Control
Reg.
Addr
(Hex) Bit(s) Name
B00
B01
B02
B02
B03
[0]
[0]
[0]
[1]
[0]
[0]
[7:0] EEPROM Buffer
STATUS_EEPROM
(read-only)
EEPROM
data error
(read-only)
Soft_EEPROM
Enable EEPROM
write
REG2EEPROM
IO_UPDATE
Segment Register 1
to EEPROM Buffer
Segment Register 23
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not need to be set back to 0.
[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Description
This read-only register indicates the status of the data transferred between the EEPROM and the buffer
register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin
when 0x01D[7] is set.
[0] = 0; data transfer is done.
[0] = 1; data transfer is not done.
This read-only register indicates an error during the data transferred between the EEPROM and the buffer.
[0] = 0; no error. Data is correct.
[0] = 1; incorrect data detected.
When the EEPROM pin is tied low, setting Soft_EEPROM resets the AD9522 using the settings saved
in EEPROM.
[1] = 1; soft reset with EEPROM settings (self-clearing). This bit self-clears on the next serial port clock
cycle after the completion of writing to this register.
Enables the user to write to the EEPROM.
[0] = 0; EEPROM write protection is enabled. User cannot write to EEPROM (default).
[0] = 1; EEPROM write protection is disabled. User can write to EEPROM.
Transfers data from the buffer register to the EEPROM (self-clearing).
[0] = 1; setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process);
it is reset by the I²C master after the data transfer is done.
Description
Description
The EEPROM buffer segment section stores the starting address and number of bytes that are to be
stored and read back to and from the EEPROM. Because the AD9522 register space is noncontiguous,
the EEPROM controller needs to know the starting address and number of bytes in the AD9522 register
space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM
controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM
buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such
that all registers are transferred to/from the EEPROM, and an IO_UPDATE is issued after transfer. See the
Programming the EEPROM Buffer Segment section for more information.
Rev. 0 | Page 72 of 76