AD9600BCPZ-105 Analog Devices Inc, AD9600BCPZ-105 Datasheet - Page 10

• Manufacturer Part Number: AD9600BCPZ-105
• Description: IC,A/D CONVERTER,DUAL,10-BIT,CMOS,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9600BCPZ-105

• Number Of Bits: 10
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 650mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9600
TIMING CHARACTERISTICS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
SPORT TIMING REQUIREMENTS
TIMING DIAGRAMS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CSSCLK
SSCLKSDO
SSCLKSDFS
CH A/CH B DATA
CH A/CH B FAST
DCOA/DCOB
DETECT
CLK+
CLK–
Conditions
Setup time between SYNC and the rising edge of CLK+
Hold time between SYNC and the rising edge of CLK+
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
Delay from the rising edge of CLK+ to the rising edge of SMI SCLK
Delay from the rising edge of SMI SCLK to SMI SDO
Delay from the rising edge of SMI SCLK to SMI SDFS
N – 13
N – 3
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing
N
t
S
t
t
A
PD
N – 12
N – 2
N + 1
t
CLK
t
H
N – 11
N + 2
N – 1
Rev. B | Page 10 of 72
N – 10
N + 3
N
t
DCO
N – 9
N + 1
N + 4
N – 8
N + 2
N + 5
t
CLK
N + 6
N + 3
N – 7
N + 7
N – 6
N + 4
N + 8
N – 5
N + 5
Min
2
2
40
2
2
10
10
10
10
3.2
−0.4
−0.4
N – 4
N + 6
Typ
0.24
0.40
4.5
0
0
Max
6.2
0.4
0.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns