AD9629-40EBZ Analog Devices Inc, AD9629-40EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9629-40EBZ
• Description: 12 Bit 40 Msps Low Pwr ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9629-40EBZ

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 60.5mW @ 40MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9629
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9629
Addr
(Hex)
0x14
0x15
0x16
0x17
0x19
0x1A
0x1B
0x1C
0x24
0x2A
1.1. AD9629 Specific Customer SPI Control
0x101
Register Name
Output mode
Output adjust
Output phase
Output delay
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
BIST signature LSB
OR/MODE select
USR2
Bit 7
(MSB)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
DCO
Output
polarity
0 =
normal
1 =
inverted
Enable
DCO
delay
B7
B15
B7
B15
Open
1
Bit 6
Open
Open
B6
B14
B6
B14
Open
Open
Bit 5
Open
1.8 V DCO
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
Open
Enable
data
delay
B5
B13
B5
B13
Open
Open
BIST signature, Bits[7:0]
Bit 4
Output
disable
Open
B4
B12
B4
B12
Open
Open
Rev. 0 | Page 28 of 32
Open
Bit 3
Open
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Open
B3
B11
B3
B11
Open
Enable
GCLK
detect
Bit 2
Output
invert
B2
B10
B2
B10
Open
Run GCLK
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
001 = 1 input clock cycle
DCO/data delay, Bits[2:0]
cycles of phase delay)
000 = no delay
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
Bit 1
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
B1
B9
B1
B9
Open
Open
Bit 0
(LSB)
B0
B8
B0
B8
0 =
MODE
1 = OR
(default)
Disable
SDIO
pull-
down
Default
Value
(Hex)
0x00
0x22
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x88
Comments
Configures the
outputs and the
format of the data
Determines CMOS
output drive
strength properties
On devices that
utilize global clock
divide, determines
which phase of the
divider output is
used to supply the
output clock;
internal latching is
unaffected
Sets the fine output
delay of the output
clock, but does not
change internal
timing
User-defined
pattern, 1 LSB
User-defined
pattern, 1 MSB
User-defined
pattern, 2 LSB
User-defined
pattern, 2 MSB
Least significant byte
of BIST signature,
read only
Selects I/O
functionality in
conjunction w/
Address 0x08 for
MODE (input) or OR
(output) on external
Pin 23
Enables internal
oscillator for clock
rates of <5 MHz